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fujitsu semiconduc t or cont r oller man u al f 2 mc-8l 8 - b it m ic rocon tr oll er mb89980 s er ies h ardware manual cm25-10141-1e

fujitsu limited f 2 mc-8l 3 2 -b it m i cr o c on t ro ll er mb89980 series h ardware manual

i preface n objective and intended readership of this manual the mb89980 series has been developed as a general-purpose version of the f 2 mc*-8l family consisting of proprietary 8-bit, single-chip microcontrollers. the mb89980 series is applicable to a wide range of applications from welfare products to industrial equipment, including portable devices. this manual describes the functions and operation of the mb89980 series and is aimed at engineers using the mb89980 series of microcontrollers to develop actual products. see the f 2 mc-8l mb89600 series programming manual for details on the mb89980 instruction set. *: f 2 mc stands for fujitsu flexible microcontroller. n configuration of this manual this manual consists of the following 15 chapters: chapter 1 "overview" provides an overview of the features and functions of the mb89980 series. chapter 2 "handling devices" describes points to note when using the mb89980 series. chapter 3 "cpu" describes the functions of the mb89980 series cpu. chapter 4 "i/o ports" describes the function and operation of the mb89980 series i/o ports. chapter 5 "timebase timer" describes the function and operation of the mb89980 series timebase timer. chapter 6 "watchdog timer" describes the functions and operation of the mb89980 series watchdog timer. chapter 7 "8-bit pwm timer (pwm timer 1, pwm timer 2)" describes the functions and operation of the mb89980 series 8-bit pwm timer. chapter 8 "8/16-bit timer/counter" describes the functions and operation of the mb89980 series 8/16-bit timer/counter. chapter 9 "external interrupt circuit 1 (edge-triggered)" describes the functions and operation of the mb89980 series external interrupt circuit 1 (edge-triggered interrupt). chapter 10 "external interrupt circuit 2 (level-triggered)" describes the functions and operation of the mb89980 series external interrupt circuit 2 (level-triggered interrupt). chapter 11 "a/d converter" describes the functions and operation of the mb89980 series a/d converter.
ii chapter 12 "watch prescaler" describes the functions and operation of the mb89980 series watch prescaler. chapter 13 "remote control generator (6-bit ppg)" describes the functions and operation of the mb89980 series remote control transmission output. chapter 14 "lcd controller-driver" describes the functions and operation of the mb89980 series liquid crystal display (lcd) controller-driver circuit. chapter 15 "buzzer output" describes the function and operation of the mb89980 series audible alarm output. appendix the appendices include the i/o map, mask options, instruction summary, instruction list, and instruction map.
iii ?2000 fujitsu limited printed in japan 1. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. 2. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. 3. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. 4. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. 5. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. 6. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.
iv reading this manual n page layout in this manual, an entire section is presented on a single page or spread whenever possible. the reader can thus view a section without having to flip pages. the content of each section is summarized immediately below the title. you can obtain a rough overview of this product by reading through these summaries. also, higher level section headings are given in lower sections so that you can know to which section the text you are currently reading belongs. n finding information in addition to the standard table of contents and index, the following methods are available to find information in a particular section when required. m register index information can be looked up in the register index by register name, by bit name, and by their respective abbreviations. m subheading index the sub-headings in each section (lines that start with n) are collected together in the subheading index. the subheading index provides a means of looking up information at a finer level of detail than the table of contents. n naming conventions for register name and pin name m example for description of register name and bit name by writing "1" to the sleep bit ( stbc : slp ) in the standby control register ... disable the interrupt request output ( tbtc : tbie from the timebase timer. interrupt is accepted if the interrupt is enabled ( ccr : i bit name register name abbreviation bit name abbreviation register name bit name abbreviation se tup data register name abbreviation register name abbreviation bit name abbreviation c urrent st = "1"). = "0")
v m notations for shared pins pin p25/sck many of the pins in the devices of this series are multi-function pins. (they can be switched between two or more functions under program control.) the multiple names of these pins (indicating their multiple functions) are separated by slant bars (/). n development tools and other resources required for development the following items are required for developing using the mb89980 series. contact fujitsu sales staff for the required development tools and other resources. m manuals required for development checklist manuals marked with * are provided with the products. in addition, manuals for products such as development tools are provided with the product. m software required for development checklist the model number for each software package differs depending on the operating system. see the f 2 mc development tools catalog or product guide for details. m items required for evaluation using one-time prom or eprom microcontrollers (when performing your own prom or eprom programming) checklist q ? f 2 mc-8l mb89980 series data sheet (provides electrical characteristics and various characteristic examples for the device.) q ? f 2 mc-8l mb89980 series hardware manual q ? f 2 mc-8l mb89600 series programming manual (describes the f 2 mc-8l series instruction set.) * ? f 2 mc-8l mb89600 series c compiler manual (only required when developing in c.) (describes program development in c and how to run the compiler.) * ? f 2 mc-8l mb89600 series assembler manual (describes program development in assembly language.) * ? f 2 mc-8l mb89600 series support system manual (describes how to run the macro assembler, linker, and library manager .) * ? f 2 mc-8l mb89600 series software simulator manual (only required when performing evaluation using the simulator.) (describes how to operate the software simulator.) q ? c compiler (only required when developing in c.) q ? assembler, linker, librarian q ? software simulator (only required when performing evalua tion using the simulator.) q ? emulator/debugger (only required when performing evaluation using the mb2140a series.)
vi m development tools checklist check with the supplier when using a third party development environment. m reference material ?f 2 mc development tools catalog ? microcomputer product guide package socket model fpt-64p-m03 (0.5 mm pitch) rom-64sqf-28dp-8l3 fpt-64p-m09 (0.65 mm pitch) rom-64qf2-28dp-8l4 q ? one of: mb89p985 q ? rom programmer (a programmer able to program an mbm27c256a) see the data sheet for details of recommended programmers. q ? package conversion adaptor for writing (available from sun hayato co., ltd.) q ? mb89pv980 (piggyback/evaluation device) q ? evaluation tools (main unit) (pod) (probe) mb2141a + mb2144-505+mb2144-20
vii contents chapter 1 overview ................................................................................................. 21 1.1 mb89980 series features .................................................................................................... ............... 22 1.2 mb89980 series ............................................................................................................. ..................... 24 1.3 differences between products ............................................................................................... ............. 27 1.4 block diagram of mb89980 series ........................................................................................... .......... 29 1.5 pin assignment ............................................................................................................. ....................... 31 1.6 package dimensions ......................................................................................................... .................. 34 1.7 i/o pins and pin functions ................................................................................................. ................. 38 chapter 2 handling devices ................................................................................. 47 2.1 notes on handling devices .................................................................................................. ............... 48 chapter 3 cpu ............................................................................................................. 51 3.1 memory space ............................................................................................................... ...................... 52 3.1.1 special areas ............................................................................................................ ..................... 54 3.1.2 storing 16-bit data in memory ............................................................................................ ............ 56 3.2 dedicated registers ........................................................................................................ .................... 57 3.2.1 condition code register (ccr) ............................................................................................ ......... 59 3.2.2 register bank pointer (rp) ............................................................................................... ............. 62 3.3 general-purpose registers .................................................................................................. ................ 63 3.4 interrupts ................................................................................................................. ............................ 66 3.4.1 interrupt level setting registers (ilr1, ilr2, ilr3) ..................................................................... . 67 3.4.2 interrupt processing ..................................................................................................... .................. 69 3.4.3 multiple interrupts ...................................................................................................... ..................... 72 3.4.4 interrupt processing time ................................................................................................ .............. 73 3.4.5 stack operation during interrupt processing .............................................................................. .... 75 3.4.6 stack area for interrupt processing ...................................................................................... .......... 76 3.5 resets ..................................................................................................................... ............................ 77 3.5.1 external reset pin ....................................................................................................... ................... 79 3.5.2 reset operation .......................................................................................................... ................... 80 3.5.3 pin states during reset .................................................................................................. ................ 82 3.6 clocks ..................................................................................................................... ............................. 83 3.6.1 clock generator .......................................................................................................... ................... 85 3.6.2 clock controller ......................................................................................................... ..................... 87 3.6.3 system clock control register (sycc) ..................................................................................... .... 90 3.6.4 clock modes .............................................................................................................. ..................... 93 3.6.5 oscillation stabilization delay time ..................................................................................... .......... 96 3.7 standby modes (low-power consumption) ...................................................................................... .. 98 3.7.1 operating states in standby modes ........................................................................................ ....... 99 3.7.2 sleep mode ............................................................................................................... ................... 101 3.7.3 stop mode ................................................................................................................ .................... 102 3.7.4 watch mode ............................................................................................................... .................. 104 3.7.5 standby control register (stbc) .......................................................................................... ...... 105 3.7.6 state transition diagram 1 (options: power-on reset, two clocks) ........................................... 107
viii 3.7.7 state transition diagram 2 (options: no power-on reset, two clocks) .................................... 110 3.7.8 state transition diagram 3 (one-clock option) ........................................................................... 113 3.7.9 notes on using standby modes ............................................................................................. ..... 115 3.8 memory access mode ......................................................................................................... ............. 117 chapter 4 i/o ports ................................................................................................ 119 4.1 overview of i/o ports ...................................................................................................... .................. 120 4.2 port 0 and port 1 .......................................................................................................... ..................... 123 4.2.1 port-0 and port-1 registers (pdr0, pdr1, purr0 ddr0, ddr1, purr1) .............................. 127 4.2.2 operation of port 0 and port 1 ........................................................................................... .......... 130 4.3 port 2 ..................................................................................................................... ........................... 132 4.3.1 port-2 registers (pdr2, ddr2) ............................................................................................ ...... 136 4.3.2 operation of port 2 ..................................................................................................... ................ 138 4.4 port 3 ..................................................................................................................... ........................... 140 4.4.1 port-3 register (pdr3) ................................................................................................... ............. 142 4.4.2 operation of port 3 ..................................................................................................... ................ 143 4.5 ports 4, 6 and 7 ........................................................................................................... ...................... 145 4.5.1 port-4, port-6, and port-7 registers (pdr4, pdr6, and pdr7) ................................................. 148 4.5.2 operation of port 4, port 6 and port 7 ................................................................................... ...... 150 4.6 port 5 .................................................................................................................... ........................... 152 4.6.1 port-5 register (pdr5) ................................................................................................... ............. 155 4.6.2 operation of port 5 ...................................................................................................... ................ 157 4.7 program example for i/o ports .............................................................................................. ........... 158 chapter 5 timebase timer .................................................................................... 161 5.1 overview of timebase timer ................................................................................................ ........... 162 5.2 block diagram of timebase timer ............................................................................................ ........ 164 5.3 timebase timer control register (tbtc) ..................................................................................... ... 166 5.4 timebase timer interrupt ................................................................................................... ............... 168 5.5 operation of timebase timer ................................................................................................ ........... 169 5.6 notes on using timebase timer .............................................................................................. ........ 171 5.7 program example for timebase timer ......................................................................................... .... 173 chapter 6 watchdog timer ................................................................................. 175 6.1 overview of watchdog timer ................................................................................................. ........... 176 6.2 block diagram of watchdog timer ............................................................................................ ....... 177 6.3 watchdog timer control register (wdtc) ..................................................................................... . 179 6.4 operation of watchdog timer ................................................................................................ ........... 181 6.5 notes on using watchdog timer .............................................................................................. ........ 183 6.6 program example for watchdog timer ......................................................................................... .... 184 chapter 7 8-bit pwm timer .................................................................................... 185 7.1 overview of 8-bit pwm timer ................................................................................................ ........... 186 7.2 block diagram of 8-bit pwm timer ........................................................................................... ........ 189 7.3 structure of 8-bit pwm timer 1 ............................................................................................. ........... 191 7.3.1 pwm1 control register (cntr1) ............................................................................................ .... 193 7.3.2 pwm 1 compare register (comr1) ........................................................................................... 195 7.4 structure of 8-bit pwm timer 2 ............................................................................................. ........... 197
ix 7.4.1 pwm 2 control register (cntr2) ........................................................................................... .... 199 7.4.2 pwm 2 compare register (comr2) ........................................................................................... 201 7.5 8-bit pwm timer interrupts ................................................................................................. ............... 203 7.6 operation of interval timer function ....................................................................................... .......... 204 7.7 operation of pwm timer function ............................................................................................ ........ 206 7.8 states in each mode during 8-bit pwm timer operation .................................................................. 208 7.9 notes on using 8-bit pwm timer ............................................................................................. ......... 210 7.10 program example for 8-bit pwm timer ....................................................................................... ...... 211 chapter 8 8/16-bit timer/counter ...................................................................... 215 8.1 overview of 8/16 -bit timer/counter ........................................................................................ .......... 216 8.2 block diagram of 8/16-bit timer/counter .................................................................................... ...... 219 8.3 structure of 8/16-bit timer/counter ........................................................................................ ........... 221 8.3.1 timer 1 control register (t1cr) .......................................................................................... ........ 224 8.3.2 timer 2 control register (t2cr) .......................................................................................... ........ 227 8.3.3 timer 1 data register (t1dr) ............................................................................................. ......... 229 8.3.4 timer 2 data register (t1dr) ............................................................................................. ......... 231 8.4 8/16-bit timer/counter interrupt ........................................................................................... ............. 233 8.5 operation of interval timer function ....................................................................................... .......... 235 8.6 operation of counter function .............................................................................................. ............ 237 8.7 operation of the square wave output initial setting function .......................................................... 239 8.8 operation of 8/16-bit timer/counter stop and restart ..................................................................... 241 8.9 states in each mode during 8/16-bit timer/counter operation ......................................................... 242 8.10 notes on using 8/16-bit timer/counter ..................................................................................... ........ 244 8.11 program examples for 8/16-bit timer/counter ............................................................................... ... 246 chapter 9 external interrupt circuit 1 (edge) .......................................... 251 9.1 overview of external interrupt circuit 1 ................................................................................... .......... 252 9.2 block diagram of external interrupt circuit 1 ............................................................................. ....... 253 9.3 structure of external interrupt circuit 1 .................................................................................. ........... 255 9.3.1 external interrupt 1 control register (eie1) ............................................................................. .... 258 9.3.2 external interrupt 1 flag register (eif1) ................................................................................ ...... 260 9.4 external interrupt circuit 1 interrupts .................................................................................... ............. 262 9.5 operation of external interrupt circuit 1 ................................................................................. .......... 264 9.6 program example for external interrupt circuit 1 ........................................................................... ... 266 chapter 10 external interrupt circuit 2 (level) ........................................ 269 10.1 overview of external interrupt circuit 2 .................................................................................. ........... 270 10.2 block diagram of external interrupt circuit 2 ............................................................................. ........ 271 10.3 structure of external interrupt circuit 2 ................................................................................. ............ 272 10.3.1 external interrupt 2 control register (eie2) ............................................................................ ..... 275 10.3.2 external interrupt 2 flag register (eif2) ............................................................................... ....... 277 10.4 external interrupt circuit 2 interrupt .................................................................................... ............... 278 10.5 operation of external interrupt circuit 2 ................................................................................. ........... 279 10.6 program example for external interrupt circuit 2 ......................................................................... .... 281 chapter 11 a/d converter ..................................................................................... 283 11.1 overview of a/d converter ................................................................................................ ............... 284
x 11.2 block diagram of a/d converter ............................................................................................ ........... 285 11.3 structure of a/d converter ............................................................................................... ................ 288 11.3.1 a/d control register 1 (adc1) ........................................................................................... ......... 291 11.3.2 a/d control register 2 (adc2) ........................................................................................... ......... 294 11.3.3 a/d data register (adcd) ................................................................................................ .......... 296 11.4 a/d converter interrupts .................................................................................................. ................. 297 11.5 operation of a/d converter ............................................................................................... .............. 298 11.6 notes on using a/d converter .............................................................................................. ............ 301 11.7 program example for a/d converter ......................................................................................... ....... 303 chapter 12 watch prescaler .............................................................................. 307 12.1 overview of watch prescaler ............................................................................................... ............. 308 12.2 block diagram of watch prescaler .......................................................................................... ......... 310 12.3 watch prescaler control register (wpcr) ................................................................................... ... 312 12.4 watch prescaler interrupt ................................................................................................. ................ 314 12.5 operation of watch prescaler .............................................................................................. ............. 315 12.6 notes on using watch prescaler ............................................................................................ .......... 317 12.7 program example for watch prescaler .................................................................................... ...... 318 chapter 13 remote control generator (6-bit ppg) 321 13.1 overview of remote control generator ...................................................................................... ...... 322 13.2 block diagram of remote control generator ................................................................................ .. 327 13.3 structure of remote control generator ..................................................................................... ....... 329 13.3.1 remote control register 1 (rcr1) ........................................................................................ ..... 331 13.3.2 remote control register 2 (rcr2) ........................................................................................ ..... 333 13.4 operation of remote control generator ..................................................................................... ...... 335 13.5 notes on using remote control generator .................................................................................. ... 337 13.6 program example for remote control generator ............................................................................ 339 chapter 14 lcd controller/driver ................................................................... 341 14.1 overview of lcd controller/driver ........................................................................................ ........... 342 14.2 block diagram of lcd controller/driver ................................................................................... ....... 343 14.2.1 lcd controller/driver internal divider resistors ....................................................................... . 345 14.2.2 lcd controller/driver external divider resistors ........................................................................ 348 14.3 structure of lcd controller/driver ........................................................................................ ............ 350 14.3.1 lcd control register (lcr1) ............................................................................................. ......... 354 14.3.2 lcd control register (lcr2) ............................................................................................. ......... 356 14.3.3 display ram ............................................................................................................. ................... 358 14.4 operation of lcd controller/driver ....................................................................................... ........... 360 14.4.1 output waveforms during lcd controller/driver operation (1/2 duty ratio) .............................. 362 14.4.2 output waveforms during lcd controller/driver operation (1/3 duty ratio) .............................. 365 14.4.3 output waveforms during lcd controller/driver operation (1/4 duty ratio) .............................. 368 14.5 program example for lcd controller/driver ................................................................................. .... 371 chapter 15 buzzer output .................................................................................... 373 15.1 overview of buzzer output ................................................................................................. .............. 374 15.2 block diagram of buzzer output ............................................................................................ ........... 376
xi 15.3 structure of buzzer output ................................................................................................ ................ 377 15.4 buzzer register (bzcr) .................................................................................................... ................ 378 15.5 program example for buzzer output ........................................................................................ ........ 380 appendix ...................................................................................................................... .... 381 appendix a i/o map .......................................................................................................... .................... 382 appendix b instructions ..................................................................................................... .................... 385 b.1 instruction list symbols ................................................................................................... ............... 386 b.2 addressing ................................................................................................................. ..................... 388 b.3 special instructions ....................................................................................................... .................. 392 b.4 f2mc-8l instructions ....................................................................................................... ............... 395 b.5 instruction map ............................................................................................................ .................... 406 b.6 bit manipulation instructions (setb, clrb) ................................................................................. .. 407 appendix c mask options ........................................................................................................ ................ 408 appendix d programming specifications for one-time prom and eprom microcontrollers 411 d.1 programming to the one-time prom microcontroller ................................................................... 412 d.2 programming yield and erasure .............................................................................................. ....... 414 d.3 programming to the eprom with piggyback/evaluation device .................................................... 415 appendix e mb89980 series pin states ........................................................................................... ....... 416
xii figures figure 1.4-1 mb89980 series overall block diagram .............................................................................. .... 30 figure 1.5-1 fpt-64p-m03 and fpt-64p-m09 pin assignment ................................................................... 32 figure 1.5-2 mqp-64c-p01 pin assignment ........................................................................................ ........ 33 figure 1.6-1 fpt-64p-m03 package dimensions .................................................................................... .... 35 figure 1.6-2 fpt-64p-m09 package dimensions .................................................................................... .... 36 figure 1.6-3 mqp-64c-p01 package dimensions .................................................................................... ... 37 figure 3.1-1 memory map ........................................................................................................ ..................... 53 figure 3.1-2 storing 16-bit data in memory ..................................................................................... ............. 56 figure 3.1-3 byte order of 16-bit data in an instruction ....................................................................... ........ 56 figure 3.2-1 dedicated register configuration .................................................................................. ........... 57 figure 3.2-2 structure of condition code register .............................................................................. ......... 59 figure 3.2-3 change of carry flag by shift instruction ......................................................................... ........ 60 figure 3.2-4 structure of register bank pointer ................................................................................ ........... 62 figure 3.2-5 rule for conversion of actual addresses of general-purpose register area .......................... 62 figure 3.3-1 register bank structure ........................................................................................... ................. 64 figure 3.4-1 structure of interrupt level setting registers .................................................................... ....... 67 figure 3.4-2 interrupt processing .............................................................................................. .................... 70 figure 3.4-3 example of multiple interrupts .................................................................................... .............. 72 figure 3.4-4 interrupt processing time ......................................................................................... ................ 73 figure 3.4-5 stack operation at start of interrupt processing .................................................................. .... 75 figure 3.4-6 stack area for interrupt processing ............................................................................... ........... 76 figure 3.5-1 block diagram of external reset pin ............................................................................... ......... 79 figure 3.5-2 reset operation flow diagram ...................................................................................... .......... 80 figure 3.6-1 clock supply map .................................................................................................. ................... 84 figure 3.6-2 connection example for a crystal or ceramic resonator ........................................................ 85 figure 3.6-3 connection example for cr ......................................................................................... ............ 86 figure 3.6-4 connection example for external clock ............................................................................. ...... 86 figure 3.6-5 block diagram of clock controller ................................................................................. ........... 88 figure 3.6-6 structure of system clock control register (sycc) ................................................................ 90 figure 3.6-7 operation of oscillator after starting oscillation ................................................................ ....... 96 figure 3.7-1 standby control register (stbc) ................................................................................... ........ 105 figure 3.7-2 state transition diagram 1 (options: power-on reset, two clocks) ..................................... 107 figure 3.7-3 state transition diagram 2 (options: without power-on reset, two clocks) ........................ 110 figure 3.7-4 state transition diagram 3 (products with power-on reset) ................................................. 113 figure 3.7-5 state transition diagram 3 (products without power-on reset) ............................................ 113
xiii figure 3.8-1 mode data structure ............................................................................................... ................ 117 figure 3.8-2 memory access selection operation ................................................................................. ..... 118 figure 4.2-1 block diagram of port-0 and port-1 pin for mb89983 ............................................................. 12 5 figure 4.2-2 block diagram of port-0 and port-1 pin for mb89p985 and mb89pv980 .............................. 125 figure 4.2-3 pull up control registers setting (purr0) ......................................................................... ....... 129 figure 4.2-4 pull up control registers setting (purr0, purr1) .................................................................. 129 figure 4.3-1 block diagram of port-2 pin for mb89983 ........................................................................... .... 134 figure 4.3-2 block diagram of port-2 pin for mb89p985 and mb89pv980 ................................................ 134 figure 4.4-1 block diagram of port-3 pin ....................................................................................... ............. 141 figure 4.5-1 block diagram of port-4, 6 and 7 for mb89983 ...................................................................... . 146 figure 4.5-2 block diagram of port-4, 6 and 7 for mb89p985 and mb89pv980 ........................................ 147 figure 4.6-1 block diagram of port-5 for mb89983 ............................................................................... ...... 153 figure 4.6-2 block diagram of port-5 for mb89p985 and mb89pv980 ...................................................... 153 figure 4.6-3 pull up control registers setting (purr5) ......................................................................... ....... 156 figure 4.7-1 connection example for an eight segment led ..................................................................... 1 58 figure 5.2-1 block diagram of timebase timer ................................................................................... ....... 164 figure 5.3-1 timebase timer control register (tbtc) ............................................................................ ... 166 figure 5.5-1 interval timer function settings .................................................................................. ............ 169 figure 5.5-2 operation of timebase timer ....................................................................................... ........... 170 figure 5.6-1 effect on buzzer output of clearing timebase timer ............................................................. 17 2 figure 6.2-1 block diagram of watchdog timer ................................................................................... ....... 177 figure 6.3-1 watchdog timer control register (wdtc) ............................................................................ .. 179 figure 6.4-1 watchdog timer clear and interval time ............................................................................ .... 182 figure 7.1-1 example d/a converter configuration using pwm output and low pass filter .................... 188 figure 7.2-1 block diagram of 8-bit pwm timer .................................................................................. ....... 189 figure 7.3-1 block diagram of 8-bit pwm timer pin .............................................................................. ..... 191 figure 7.3-2 8-bit pwm1 timer registers ........................................................................................ ........... 192 figure 7.3-3 pwm1 control register (cntr 1) .................................................................................... ...... 193 figure 7.3-4 pwm 1 compare register (comr1) .................................................................................... .. 195 figure 7.4-1 block diagram of 8-bit pwm timer 2 pin for mb89983 .......................................................... 197 figure 7.4-2 block diagram of 8-bit pwm timer 2 pin for mb89p985 and mb89pv980 ............................ 198 figure 7.4-3 8-bit pwm timer 2 registers ....................................................................................... ........... 198 figure 7.4-4 pwm 2 control register (cntr2) ................................................................................... ...... 199 figure 7.4-5 pwm2 compare register (comr2) ..................................................................................... .. 201 figure 7.6-1 interval timer function settings .................................................................................. ............ 204 figure 7.6-2 operation of 8-bit pwm timer ...................................................................................... ........... 204 figure 7.7-1 pwm timer function settings ....................................................................................... .......... 206 figure 7.7-2 example of pwm waveform output (pto pin) ....................................................................... 20 6
xiv figure 7.8-1 counter operation during standby modes or operation halt (for interval timer function) .. 208 figure 7.8-2 operation during standby modes or operation halt (for pwm timer function) ................... 209 figure 7.9-1 error on starting counter operation ............................................................................... ........ 210 figure 8.2-1 block diagram 8/16-bit timer/counter .............................................................................. ..... 219 figure 8.3-1 block diagram of 8/16-bit timer/counter pins for mb89983 ................................................ 221 figure 8.3-2 block diagram of 8/16-bit timer/counter pins for mb89p985 and mb89pv980 .................. 222 figure 8.3-3 8/16-bit timer/counter registers .................................................................................. .......... 223 figure 8.3-4 pwc pulse width control register 1 (t1cr) ........................................................................ 224 figure 8.3-5 timer 2 control register (t2cr) ................................................................................... ......... 227 figure 8.3-6 timer 1 data register (t1dr) ...................................................................................... .......... 229 figure 8.3-7 timer 2 data register (t2dr) ...................................................................................... .......... 231 figure 8.5-1 interval timer function (timer 1) settings ........................................................................ ..... 235 figure 8.5-2 interval timer function (timer 2) settings ........................................................................ ..... 235 figure 8.5-3 operation of interval timer (timer 1) ............................................................................. ........ 236 figure 8.5-4 interval timer function settings (16-bit mode) .................................................................... ... 236 figure 8.6-1 counter function settings (8-bit mode) ............................................................................ ..... 237 figure 8.6-2 counter function settings (16-bit mode) ........................................................................... ..... 238 figure 8.6-3 operation of counter function in 16-bit mode ...................................................................... .. 238 figure 8.7-1 square wave output initial setting equivalent circuit ............................................................ 239 figure 8.7-2 square wave output initial setting operation ...................................................................... .. 240 figure 8.9-1 counter operation during subclock mode, standby mode, or operation halt ....................... 243 figure 8.10-1 operation when timer stop bit is used ............................................................................ ...... 244 figure 8.10-2 error on starting counter operation .............................................................................. ......... 245 figure 9.2-1 block diagram of external interrupt circuit 1 ..................................................................... ..... 253 figure 9.3-1 block diagram of external interrupt circuit 1 pins for mb89983 ............................................ 256 figure 9.3-2 block diagram of external interrupt circuit 1 pins for mb89p985 and mb89pv980 ............. 256 figure 9.3-3 external interrupt circuit 1 registers ............................................................................ .......... 257 figure 9.3-4 external interrupt 1 control register (eie1) ...................................................................... ..... 258 figure 9.3-5 external interrupt 1 flag register (eif1) ......................................................................... ....... 260 figure 9.5-1 external interrupt circuit 1 settings ............................................................................. ........... 264 figure 9.5-2 operation of external interrupt 1 (int10) ......................................................................... ...... 265 figure 10.2-1 block diagram of external interrupt circuit 2 .................................................................... ...... 271 figure 10.3-1 block diagram of external interrupt circuit 1 pins for mb89983 ............................................ 273 figure 10.3-2 block diagram of external interrupt circuit 2 pins for mb89p985 and mb89pv980 ............. 273 figure 10.3-3 external interrupt circuit 2 registers ........................................................................... ........... 274 figure 10.3-4 external interrupt 2 control register (eie2) ..................................................................... ...... 275 figure 10.3-5 external interrupt 2 flag register (eif2) ........................................................................ ........ 277 figure 10.5-1 external interrupt circuit 2 settings ............................................................................ ............ 279
xv figure 10.5-2 operation of external interrupt 2 (int20) ........................................................................ ........ 280 figure 11.2-1 block diagram of a/d converter ................................................................................... .......... 285 figure 11.3-1 block diagram of p53/an3 to p50/an0 pins for mb89983 ..................................................... 288 figure 11.3-2 block diagram of p53/an3 to p50/an0 pins for mb89p985 and mb89pv980 ...................... 289 figure 11.3-3 a/d converter registers .......................................................................................... ................ 289 figure 11.3-4 a/d control register 1 (adc1) .................................................................................... ............ 291 figure 11.3-5 a/d control register 2 (adc2) .................................................................................... ............ 294 figure 11.3-6 a/d data register (adcd) ......................................................................................... ............. 296 figure 11.5-1 a/d conversion function (software activation) settings ........................................................ 29 8 figure 11.5-2 a/d conversion function (continuous activation) settings .................................................... 298 figure 11.5-3 sense function (software activation) settings .................................................................... ... 299 figure 11.5-4 sense function (continuous activation) settings .................................................................. . 299 figure 11.6-1 analog input equivalent circuit .................................................................................. ............. 301 figure 12.2-1 block diagram of watch prescaler ................................................................................. ......... 310 figure 12.3-1 watch prescaler control register (wpcr) .......................................................................... ... 312 figure 12.5-1 interval timer function settings ................................................................................. ............. 315 figure 12.5-2 operation of watch prescaler ..................................................................................... ............ 316 figure 13.2-1 block diagram of remote control generator ........................................................................ .. 327 figure 13.3-1 block diagram of p24/rco pin for mb89983 ......................................................................... 329 figure 13.3-2 block diagram of p24/rco pin for mb89p985 and mb89pv980 .......................................... 330 figure 13.3-3 remote control transmit generator registers ...................................................................... . 330 figure 13.3-4 remote control register 1 (rcr1) ................................................................................. ........ 331 figure 13.3-5 remote control register 2 (rcr2) ................................................................................. ........ 333 figure 13.4-1 remote control generator settings ................................................................................ ........ 335 figure 13.4-2 operation of remote control generator ............................................................................ ..... 336 figure 13.5-1 changing settings during operation (remote control) ........................................................... 33 8 figure 13.5-2 error during activating operation (remote control) ............................................................... . 338 figure 14.2-1 block diagram of lcd controller/driver ........................................................................... ....... 343 figure 14.2-2 internal voltage divider equivalent circuit ...................................................................... ........ 345 figure 14.2-3 use of internal voltage divider resistors ........................................................................ ........ 346 figure 14.2-4 use of internal voltage divider resistors with brightness adjustment ................................... 347 figure 14.2-5 external voltage divider resistor connections .................................................................... ... 348 figure 14.2-6 external voltage divider resistor connections .................................................................... ... 349 figure 14.3-1 block diagram of lcd controller/driver pin (dedicated common output pins) .................... 350 figure 14.3-2 block diagram of lcd controller-driver pin for mb89983 (dual function common/segment output pins) 351 figure 14.3-3 block diagram of lcd controller-driver pin for mb89p985 and mb89pv980 (dual function common/segment output pins) 352 figure 14.3-4 lcd controller/driver register ................................................................................... ............. 353
xvi figure 14.3-5 lcdc control register 1 (lcr1) ................................................................................... ........ 354 figure 14.3-6 lcd control register 2 (lcr2) .................................................................................... .......... 356 figure 14.3-7 segment/common output pins and corresponding display ram ......................................... 358 figure 14.4-1 lcd controller/driver settings ................................................................................... ............ 360 figure 14.4-2 output waveforms, 1/2 bias and 1/2 duty ratio example ..................................................... 363 figure 14.4-3 segment/common connections, data states and corresponding display ............................ 364 figure 14.4-4 output waveforms, 1/3 bias and 1/3 duty ratio example ..................................................... 366 figure 14.4-5 segment/common connections, data states and corresponding display ............................ 367 figure 14.4-6 output waveforms, 1/3 bias and 1/4 duty ratio example ..................................................... 369 figure 14.4-7 segment/common connections, data states and corresponding display ............................ 370 figure 15.2-1 block diagram of buzzer output ................................................................................... ......... 376 figure 15.3-1 block diagram of p30/pwm1/bz pin ................................................................................. .... 377 figure 15.3-2 buzzer output register ........................................................................................... ............... 377 figure 15.4-1 buzzer register (bzcr) ........................................................................................... .............. 378 figure b.2-1 direct addressing ................................................................................................. .................. 388 figure b.2-2 extended addressing ............................................................................................... ............... 388 figure b.2-3 bit direct addressing ............................................................................................. ................. 389 figure b.2-4 index addressing .................................................................................................. .................. 389 figure b.2-5 pointer addressing ................................................................................................ ................. 389 figure b.2-6 general-purpose register addressing ............................................................................... .... 389 figure b.2-7 immediate addressing .............................................................................................. .............. 390 figure b.2-8 vector addressing ................................................................................................. ................. 390 figure b.2-9 relative addressing ............................................................................................... ................. 391 figure b.2-10 inherent addressing .............................................................................................. .................. 391 figure b.3-1 jmp @a ............................................................................................................ ...................... 392 figure b.3-2 movw a,pc ......................................................................................................... .................. 392 figure b.3-3 mulu a ............................................................................................................ ...................... 393 figure b.3-4 divu a ............................................................................................................ ........................ 393 figure b.3-5 xchw a,pc ......................................................................................................... .................. 393 figure b.3-6 example using xchw a, pc .......................................................................................... ....... 394 figure b.3-7 execution example of callv #3 ..................................................................................... ....... 394 figure d.1-1 memory map in eprom mode .......................................................................................... ..... 412 figure d.1-2 screening procedure ............................................................................................... ............... 413 figure d.3-1 memory map of piggyback/evaluation device ....................................................................... 4 15
xvii tables table 1.2-1 mb89980 series product lineup ...................................................................................... ......... 24 table 1.2-2 mb89980 series cpu and peripheral functions ...................................................................... 2 5 table 1.3-1 package and corresponding products ................................................................................. ..... 27 table 1.7-1 pin description .................................................................................................... ...................... 38 table 1.7-2 i/o circuit type ................................................................................................... ....................... 42 table 3.1-1 general-purpose register areas ..................................................................................... .......... 54 table 3.1-2 vector table ....................................................................................................... ....................... 55 table 3.2-1 interrupt level .................................................................................................... ....................... 61 table 3.4-1 interrupt request and interrupt vector ............................................................................. ......... 66 table 3.4-2 interrupt level setting bit and interrupt level .................................................................... ....... 67 table 3.5-1 reset source ....................................................................................................... ...................... 77 table 3.5-2 reset source and oscillation stabilization delay time ............................................................. 78 table 3.6-1 system clock control register (sycc) bits .......................................................................... ... 91 table 3.6-2 clock mode operating states ........................................................................................ ............ 93 table 3.6-3 main clock startup conditions vs. oscillation stabilization delay time ................................... 97 table 3.7-1 operating states of the cpu and peripheral functions in standby modes .............................. 99 table 3.7-2 standby control register (stbc) bits ............................................................................... ..... 106 table 3.7-3 changing to/wake-up from clock modes (options: power-on reset, two clocks) ................ 108 table 3.7-4 changing to/wake-up from standby modes (options: power-on reset, two clocks) ............ 109 table 3.7-5 changing to/wake-up from clock modes (options: without power-on reset, two clocks) .. 111 table 3.7-6 changing to/wake-up from standby modes (options: without power-on reset, two clocks) .... 112 table 3.7-7 changing to main clock mode run state and reset (one-clock option) .............................. 114 table 3.7-8 changing to/wake-up from standby modes (options: power-on reset, two clocks) ............ 114 table 3.7-9 standby control register (stbc) low-power consumption mode settings .......................... 116 table 3.8-1 mode pin setting ................................................................................................... .................. 117 table 3.8-2 mode pins and mode data ............................................................................................ .......... 118 table 4.1-1 port function ...................................................................................................... ..................... 121 table 4.1-2 port registers ..................................................................................................... ..................... 122 table 4.2-1 port-0 and port-1 pins ............................................................................................. ................ 124 table 4.2-2 correspondence between pin and register for port-0 and port-1 .......................................... 126 table 4.2-3 port-0 and port-1 register function ................................................................................ ........ 127 table 4.2-4 port-0 and port-1 pin state ........................................................................................ ............. 131 table 4.3-1 port-2 pin ......................................................................................................... ....................... 133 table 4.3-2 correspondence between pin and register for port 2 ............................................................ 135
xviii table 4.3-3 port-2 register function ........................................................................................... .............. 137 table 4.3-4 port-0 and port-1 pin state ........................................................................................ ............. 139 table 4.4-1 port-3 pin ......................................................................................................... ....................... 140 table 4.4-2 correspondence between pin and register for port 3 ........................................................... 141 table 4.4-3 port-3 register function ........................................................................................... .............. 142 table 4.4-4 port-3 pin state ................................................................................................... ................... 144 table 4.5-1 port-4, 6, and 7 pin ............................................................................................... .................. 146 table 4.5-2 correspondence between pin and register for port 4, 6, and 7 ............................................ 147 table 4.5-3 port-4, port-6, and port-7 register function ....................................................................... ... 148 table 4.5-4 port-4, 6, and 7 pin state ......................................................................................... .............. 151 table 4.6-1 port-5 pin ......................................................................................................... ....................... 152 table 4.6-2 correspondence between pin and register for port 5 ........................................................... 154 table 4.6-3 port-4, port-6, and port-7 register function ....................................................................... ... 155 table 4.6-4 port-5 pin state ................................................................................................... ................... 157 table 5.1-1 timebase timer interval time ....................................................................................... ........... 162 table 5.1-2 clocks supplied by timebase timer .................................................................................. .... 163 table 5.3-1 timebase timer control register (tbtc) bits ....................................................................... 167 table 5.4-1 register and vector table for timebase timer interrupt ....................................................... 168 table 6.1-1 watchdog timer interval time ....................................................................................... ......... 176 table 6.3-1 watchdog timer control register (wdtc) bits ..................................................................... 18 0 table 7.1-1 interval time and square wave output range ...................................................................... 18 6 table 7.1-2 available pwm wave cycle for pwm timer function ........................................................... 187 table 7.3-1 pwm 1 control register (cntr1) bit ................................................................................. .... 194 table 7.4-1 pwm 2 control register (cntr2) bits ................................................................................ ... 200 table 7.5-1 registers and vector tables for 8-bit pwm timer interrupts ................................................. 203 table 8.1-1 timer 1 interval times and square wave frequencies in 8-bit mode .................................... 216 table 8.1-2 timer 2 interval times and square wave frequencies in 8-bit mode ................................... 217 table 8.1-3 interval times and square wave frequencies 16-bit mode ................................................... 217 table 8.3-1 timer 1 control register (t1cr) bits ............................................................................... ...... 225 table 8.3-2 timer 2 control register (t2cr) bits ............................................................................... ...... 228 table 8.4-1 8/16-bit timer/counter interrupt control bits and interrupts ................................................... 233 table 8.4-2 registers and vector table for 8/16-bit timer/counter interrupt ............................................ 234 table 8.7-1 square wave output initial setting procedure (t1cr register) ............................................ 239 table 8.8-1 timer stop and restart ............................................................................................. .............. 241 table 9.3-1 external interrupt circuit 1 pins .................................................................................. ............ 255 table 9.3-2 external interrupt 1 control register (eie1) bits vs. interrupts pins ...................................... 258 table 9.3-3 external interrupt 1 control register (eie1) bits .................................................................. .. 259 table 9.3-4 external interrupt 1 flag register (eif1) bits ..................................................................... .... 260
xix table 9.3-5 external interrupt 1 control register (eie1) bits .................................................................. ... 261 table 9.4-1 register and vector table for external interrupt circuit 1 interrupts ....................................... 263 table 10.3-1 external interrupt circuit 2 pins ................................................................................. .............. 272 table 10.3-2 external interrupt 2 control register (eie2) bits vs. pins ....................................................... 275 table 10.3-3 external interrupt 1 control register (eie1) bits ................................................................. .... 276 table 10.3-4 external interrupt 1 control register (eie1) bits ................................................................. .... 277 table 10.4-1 registers and vector table for external interrupt circuit 2 interrupts ..................................... 278 table 11.3-1 a/d control register 1 (adc1) bitss ............................................................................... ........ 292 table 11.3-2 a/d control register 1 (adc1) bitss ............................................................................... ........ 295 table 11.3-3 example of adcd register setting for sense function .......................................................... 296 table 11.4-1 register and vector table for a/d converter interrupt ........................................................... 2 97 table 12.1-1 watch prescaler interval time ..................................................................................... ........... 308 table 12.1-2 clocks supplied by watch prescaler ................................................................................ ....... 309 table 12.3-1 watch prescaler control register (wpcr) bits ...................................................................... 313 table 12.4-1 register and vector for watch prescaler interrupt. ................................................................ . 314 table 13.1-1 output cycles and "h" pulse width ranges .......................................................................... . 322 table 13.1-2 6-bit ppg resolution and output cycles (0.5 tinst count clock) ............................................. 324 table 13.1-3 6-bit ppg resolution and output cycles (0.5 tinst count clock) ............................................. 325 table 13.3-1 remote control register 1 (rcr1) bits ............................................................................. ..... 332 table 13.3-2 remote control register 2 (rcr2) bits ............................................................................. ..... 334 table 14.1-1 bias and duty ratio combinations .................................................................................. ........ 342 table 14.2-1 lcd drive voltages and biasing modes .............................................................................. ... 348 table 14.3-1 lcdc control register (lcr1) bit functions ........................................................................ . 355 table 14.3-2 lcd control register 2 (lcr2) bit functions ....................................................................... .. 357 table 14.3-3 segment outputs, display ram locations, and sharing port pins ........................................ 359 table 14.3-4 common outputs and display ram bits used in each duty ratio mode .............................. 359 table 14.4-1 display ram contents example ...................................................................................... ....... 362 table 14.4-2 display ram contents example ...................................................................................... ....... 365 table 14.4-3 display ram contents example ...................................................................................... ....... 368 table 15.1-1 output frequency .................................................................................................. .................. 374 table 15.4-1 buzzer register (bzcr) bits ....................................................................................... ............ 379 table a-1 i/o map .............................................................................................................. ...................... 382 table b.1-1 instruction list symbols ........................................................................................... ................ 386 table b.1-2 instruction list columns ........................................................................................... ............... 387 table b.2-1 vector table address corresponding to "vct" ........................................................................ . 390 table b.4-1 transfer instructions .............................................................................................. .................. 395 table b.4-2 arithmetic opeation instructions ................................................................................... ........... 399 table b.4-3 branch instructions ................................................................................................ .................. 403
xx table b.4-4 other instructions ................................................................................................. .................. 405 table b.5-1 f2mc-8l instruction map ............................................................................................ ........... 406 table b.6-1 bus operation for bit manipulation instructions .................................................................... .. 407 table c-1 mask options ......................................................................................................... ................. 408 table c-2 mask options (segment options) ....................................................................................... .... 409 table c-3 version number ....................................................................................................... ............... 410 table c-4 ordering information ................................................................................................. .............. 410 table d.1-1 eprom programmer socket adaptor .................................................................................... 412 table d.3-1 programming socket adaptor ......................................................................................... ........ 415 table e-1 pin states in each mode .............................................................................................. .......... 416
21 chapter 1 overview this chapter describes the main features and basic specifications of the mb89980 series. 1.1 "mb89980 series features" 1.2 "mb89980 series" 1.3 "differences between products" 1.4 "block diagram of mb89980 series" 1.5 "pin assignment" 1.6 "package dimensions" 1.7 "i/o pins and pin functions"
22 chapter 1 overview 1.1 mb89980 series features the mb89980 series is a line of the general-purpose, single-chip microcontrollers. in addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as an lcd controller/driver, an a/d converter, timers, pwm timers, remote control output, buzzer output and external interrupts. n mb89980 series features m various package options ? qfp package (0.65-mm lead pitch) ? lqfp package (0.5-mm lead pitch) m high speed processing at low voltage minimum execution time: 0.95 m s/4.2 mhz m f 2 mc-8l family cpu core instruction set optimized for controllers ? multiplication and division instructions ? 16-bit arithmetic operations ? test and branch instructions ? bit manipulation instructions, etc. m dual-clock control system ? main clock: max. 4.2 mhz (four selectable speeds; oscillation stopped in subclock mode.) ? subclock: 32.768 khz (operating clock used in subclock mode) m six types of timers ? 8-bit pwm timer 1 (also usable as an interval timer) ? 8-bit pwm timer 2 (also usable as an interval timer) ? 8/16-bit timer/counter (8 bits 2 channels or 16 bits 1 channel) ? 21-bit timebase timer ? watch prescaler (15 bits) m a/d converter ? sense function enabling voltage comparison at 11.4 m s ( at 4.2 mhz). ? activation by an 8/16-bit timer/counter output capable m lcd controller/driver ? 14 segments 4 commons (max. 56 pixels).
23 1.1 mb89980 series features m buzzer output ? output frequency: 1025 hz, 2051 hz, 4102 hz, 8203 hz/4.2 mhz for main clock ? 1024 hz, 2048 hz, 4096 hz/32.768 khz for subclock m remote control transmission output ? program-selectable pulse width and period. m external interrupts (wake-up function) ? external interrupt 1 (4 channels) four channels are independent and capable of wake-up from low-power consumption modes (with an edge detection function). ? external interrupt 2 (8 inputs, 1 channel) eight channels are independent and capable of wake-up from low-power consumption modes (with a "l" level detection function). m standby modes (low power modes) ? stop mode (if in sub mode, oscillation stops to minimize the current consumption.) ? sleep mode (the cpu stops to reduce the current consumption to approx. 1/3 of normal.) ? watch mode (everything except the watch prescaler stops to reduce the power consumption to an extremely low level.) m i/o ports: max. 47 channels ? general-purpose i/o ports (n-ch open-drain): 8 ? output-only ports (n-ch open-drain): 20 ? general-purpose i/o ports (cmos): 16 ? input-only ports (cmos): 2 ? output-only ports (cmos): 1
24 chapter 1 overview 1.2 mb89980 series the mb89980 series contains 3 type of products. table 1.2-1 "mb89980 series product lineup" lists the product lineup and table 1.2-2 "mb89980 series cpu and peripheral functions" lists the cpu and peripheral functions. n mb89980 series product lineup table 1.2-1 mb89980 series product lineup parameter part number mb89983 mb89p985 mb89pv980 classification mask rom otp piggyback rom size 8k 8 bits (internal rom) 16k 8 bits (internal rom) 32k 8 bits (external rom) ram size 256 8 bits 512 8 bits 512 8 bits low-power consumption (stand by modes) sleep mode, stop mode, and watch mode process cmos operating voltage 2.7 v to 6.0 v 3.5 v to 6.0 v when using the a/d converter
25 1.2 mb89980 series table 1.2-2 mb89980 series cpu and peripheral functions parameter specification cpu funtions number of instructions: instruction bit length: instruction length: data bit length: minimum execution time: interrupt processing time: 136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.95 m s to 15.2 m s/4.2 mhz, 61.0 m s/32.768 khz 8.6 m s to 137.1 m s/4.2 mhz, 549.3 m s/32.768 khz p e r i p h e r a l f u n c t i o n s ports general-purpose i/o ports (n-ch open-drai) output-only ports (n-ch open-drain) general-purpose i/o ports (cmos) input-only ports (cmos) output-only ports (cmos) total 8 (4 ports also serve as peripherals, 3 ports are heavy-current drive type.) 20 (4 ports also serve as a/d, 14 ports serve as segment pins and 2 ports serve as common pins, 10 ports are heavy-current drive) 16 (12 ports also serve as an external interrupt, ) 2 (serve with sub-clock pins) 1 (serves as peripherials 47 (max.) 21-bit timebase timer 21 bits interrupt cycle: 1.95 ms, 7.80 ms, 62.41 ms, 998.64 ms/4.2 mhz for main clock watchdog timer reset generate cycle: min. 998.6 ms/4.2 mhz for main clock min. 500 ms/32.768 khz for subclock 8-bit pwm timer 1, pwm timer 2 8-bit interval timer operation (square wave output capable, operating clock cycle: 0.95 m s to 249.7 ms) 8-bit resolution pwm operation (conversion cycle: 243.8 m s to 63.9 s) 8/16-bit timer/counter output for counter clock selectability 8/16-bit timer/counter can be operated either as a 2-channel 8-bit timer/counter (timer 1 and timer 2, each with its own independent operating clock cycle), or as one 16-bit timer/ counter (operating clock cycle: 1.90 m s to 487.6 m s) in timer 1 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and square wave output capable external interrupt 1 (wake-up function) 4 independent channels (interrupt vector, request flag, request output enable) edge selectability (rising/falling) used also for wake-up from stop/sleep mode. (low-level detection is also permitted in stop mode.) external interrupt 2 (wake-up function) 8 inputs, one channel ("l" level interrupts, independent input enable). used also for wake-up from stop/sleep mode. (low-level detection is also permitted in stop mode.) 8-bit a/d converter 8-bit resolution 4 channels a/d conversion function (conversion time: 41.9 s) sense function (comparison time: 11.4 s) continuous activation by an 8/16-bit timer/counter output or a timebase timer output capable. reference voltage input (avr) watch prescaler 15 bits interrupt cycle: 31.25 ms, 0.25 s, 0.50 s, 1.00 s/32.768 khz for subclock
26 chapter 1 overview lcd controller/driver common output: 4 (max.) *1 segment output: 14 (max.) *1 lcd driving power (bias) pins: 4 lcd display ram size: 7 bytes (14 4 bits, max. 56 pixels) buzzer output output frequency: 1025 hz, 2051 hz, 4102 hz, 8203 hz/4.2 mhz for main clock 1024 hz, 2048 hz, 4096 hz/32.768 khz for subclock remote control transmit output internal 6-bit counter pulse width ("h" level pulse width of 0 m s to 1920 m s) and cycle (0.95 m s to 1920 m s) are program selectable can also be used as 6-bit ppg. note: unless otherwise specified, values given for clock cycle, conversion times, etc. are for 4.2 mhz operation, with main clock maximum clock speed selected. *1: the number of ports used for common/segment outputs is selected by mask option for mb89983 and is selected by software for mb89p985 and mb89pv980 table 1.2-2 mb89980 series cpu and peripheral functions parameter specification
27 1.3 differences between products 1.3 differences between products this section describes the differences between products in the mb89980 series and lists points to note in product selection. n differences among products and points to note for product selection o: available x: not available m memory size before evaluating using the piggyback product, verify its differences from the product that will actually be used. take particular care on the following points. (see section 3.1 "memory space."): ? on the mb89983, each general-purpose register area is limited to 0100 h to 017f h (16 banks). ? the stack area, etc., is set at the upper limit of the ram. m current consumption ? in the case of the piggyback add the current consumed by the eprom which is connected to the top socket. ? when operated at low speed, the product with a one-time prom (otprom) or an eprom will consume more current than the product with mask rom. however the current consumption in sleep/stop modes, is the same. reference: for more information about the package, see section 1.6 "package dimensions." for more information about the current consumption, see the electrical characteristics in the data sheet. m mask options functions that can be selected as options and how to designate these options vary by the product. before using, check appendix c "mask options." table 1.3-1 package and corresponding products package part number mb89983 mb89p985 mb89pv980 fpt-64p-m03 o o x fpt-64p-m09 o o x mqp-64c-p01 x x o
28 chapter 1 overview m pull-up resistor ? pull-up resisitor of mb89p985 and mb89pv980 are selected by pull-up control register (port 0, 1, 5), but there are no pull-up resistor for port 2, 4 and 6 in mb89p985 and mb89pv980. ? pull-up resistor of mb89983 are selected by mask option (port 0, 1, 2, 4, 5, 6) m segment/common port ? the segment/port, common/port output in mb89p985 and mb89pv980 are selected by lcd control register, lcr2. ? the segment/port , common/port output in mb89983 are selected by mask option.
29 1.4 block diagram of mb89980 series 1.4 block diagram of mb89980 series figure 1.4-1 "mb89980 series overall block diagram" shows the block diagram of the mb89980 series.
30 chapter 1 overview n mb89980 series block diagram figure 1.4-1 mb89980 series overall block diagram oscillator clock controller ram f 2 mc-8l cpu rom other pins mod0, mod1, v cc , v ss x 2 internal data bus 21-bit timebase 8-bit 8-bit pwm timer 2 por t 2 n-ch open-drain i/o port port 4 x0 x1 p00/int20 to p07/int27 p22/to p20/ec p27/pwm2 *1 p25 p21 *1 timer (max. 4.2 mhz) main clock reset circuit (watchdog timer) rst external interrupt 2 (wake-up funct ion) por t 0 cmos i/o por t external interrupt 1 (wake-up function) por t 1 cmos i/o port 8 8 p10/int 10 to p13/int13 4 4 4 p14 to p17 port 5 n-ch open-drain output port 8-bit a/d converter p50/an0 to p53/an3 4 4 av cc avr av ss timer/counter 1 (timer 1) 8-bit ti mer/counter 2 (timer 2 ) n-ch open-drain output ports port 6, 7 lcd controller/driver 14 4-bit display ram (7 bytes) 8-bit pwm timer 1 port 3 cmos input port ( p30 is cmos output port) p40/seg0 to p43/seg3 *1 *4 4 p44 /seg4 to p47/seg7 *1 *5 4 p60/seg8 to p61/seg9 *1 *3 2 p62/seg10 to p63/seg11 *6 2 p70/com2 to p71/com3 *3 2 com0 to com1 2 v0 to v3 4 8 6 2 p30/pwm1/bz p31/x0a* 2 p24/rco p23 p32/x1a* 2 *1: heavy -current drive type *2: when the dual clock system is selected *3, *4, *5, *6: selected using mask option in mb89983, but selected by software in mb89p985 and mb89pv980. sub-clock watch prescaler timer p26 *1 p64/seg12 to p65/seg13* 6 2 remote control output buzze r output oscillator
31 1.5 pin assignment 1.5 pin assignment figure 1.5-1 "fpt-64p-m03 and fpt-64p-m09 pin assignment" and 1.5-2 "mqp-64c-p01 pin assignment" show the pin assignment diagrams for the mb89980 series.
32 chapter 1 overview n fpt-64p-m03 and fpt-64p-m09 pin assignment figure 1.5-1 fpt-64p-m03 and fpt-64p-m09 pin assignment v1 v0 p27/pwm2* 1 p26* 1 p25 p24/rco p23 p22/to p21* 1 p20/ec p17 p16 p15 p14 p13/int13 p12/int12 p47/seg7* 1 * 4 p46/seg6* 1 * 4 p45/seg 5* 1 * 4 p44/seg4* 1 * 4 p43/seg3* 1 * 5 p42/seg2* 1 * 5 p41/seg1* 1 * 5 p40/seg0* 1 * 5 vcc p71/com3* 3 p70/com2* 3 com1 com0 v3 v2 vss p31/x0a* 2 p32/x1a* 2 rst mod0 mod1 x0 x1 vss p02/int22 p03/int23 p04/int24 p05/int25 p06/int26 p07/int27 p10/int10 p11/int11 p60/seg8* 1 * 3 p61/seg9* 1 * 3 p62/seg10* 6 p63/seg11* 6 p64/seg12* 6 p65/seg13* 6 p50/an0 p51/an1 p52/an2 p53/an3 avcc av r avss p00/int20 p01/int21 p30/pwm1/bz 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 top vie w qfp-64 (fpt-64p-m09) (fpt-64p-m03) *1: heavy-current drive type *2: when the dual clock system is selected *3, *4, *5, *6: selected using mask option in mb89983, but selected by software in mb89p985 and mb89pv980
33 1.5 pin assignment n mqp-64c-p01 pin assignment figure 1.5-2 mqp-64c-p01 pin assignment *1: heavy-current drive type *2: when the dual clock system is selected *3, *4,*5, *6: selected using mask option in mb89983, but selected by software in mb89p985 and mb89pv980. ? pin assignment on package top (mb89pv980 only) n.c.: internally connected. do not use. pin no. pin name pin no. pin name pin no. pin name pin no. pin name 65 n.c. 73 a2 81 n.c. 89 oe 66 v pp 74 a1 82 o4 90 n.c. 67a1275a083o591a11 68 a7 76 n.c. 84 o6 92 a9 69 a6 77 o1 85 o7 93 a8 70 a5 78 o2 86 o8 94 a13 71 a4 79 o3 87 ce 95 a14 72 a3 80 v ss 88a1096v cc p47/seg7 *1*4 p60/seg8 *1*3 p61/seg9 *1*3 p62/seg10 *6 p63/seg11 *6 p64/seg12 *6 p65/seg13 *6 p50/an0 p51/an1 p52/an2 p53/an3 av cc avr av ss p00/int20 p01/int21 p30/pwm1/bz p31/x0a *2 p32/x1a *2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 v2 v ss v1 v0 p27/pwm2 *1 p26 *1 p25 p24/rco p23 p22/to p21 *1 p20/ec p17 p16 p15 p14 p13/int13 p12/int12 p11/int11 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p46/seg6 *1*4 p45/seg5 *1*4 p44/seg4 *1*4 p43/seg3 *1*5 p42/seg2 *1*5 p41/seg1 *1*5 p40/seg0 *1*5 v cc p71/com3 *3 p70/com2 *3 com1 com0 v3 64 63 62 61 60 59 58 57 56 55 54 53 52 rst mod0 mod1 x0 x1 v ss p02/int22 p03/int23 p04/int24 p05/int25 p06/int26 p07/int27 p10/int10 20 21 22 23 24 25 26 27 28 29 30 31 32 85 86 87 88 89 90 91 92 93 77 76 75 74 73 72 71 70 69 94 95 96 65 66 67 68 84 83 82 81 80 79 78 (top view)
34 chapter 1 overview 1.6 package dimensions three types of package are available for mb89980 series. figure 1.6-1 "fpt-64p-m03 package dimensions" and figure 1.6-2 "fpt-64p-m09 package dimensions" shows the package dimensions. n fpt-64p-m03 package dimensions
35 1.6 package dimensions figure 1.6-1 fpt-64p-m03 package dimensions lead pitch package width length lead shape sealing method 0.5 mm 10 10 mm gull-wing plastic mold (fpt-64p-m03) 64-pin plastic lqfp c 1995 fujitsu limited f64009s-2c-5 dimension in mm (inches) 0.10(.004) .005 C .001 +.002 C 0.02 +0.05 0.127 .059 C .004 +.008 C 0.10 +0.20 1.50 "a" 0.500.20 (.020.008) details of "a" part 0 10 ? 33 32 17 16 1 64 49 48 index lead no. (stand off) 12.000.20(.472.008)sq 10.000.10(.394.004)sq 0.500.08 (.0197.0031) .007 C .001 +.003 C 0.03 +0.08 0.18 11.00 7.50 (.295) ref (.433) nom 0.100.10 (.004.004) (mounting height) 64-pin plastic lqfp (fpt-64p-m03)
36 chapter 1 overview n fpt-64p-m09 package dimensions figure 1.6-2 fpt-64p-m09 package dimensions (fpt-64p-m09) +0.20 C0.10 +.008 C.004 +0.05 C0.02 +.002 C.001 lead no. (stand off) 64 49 48 33 32 17 16 1 nom (.512) ref (.384) 13.00 9.75 (.012.004) 0.300.10 0.65(.0256)typ 12.000.10(.472.004)sq 14.000.20(.551.008)sq (.020.008) (.004.004) 0.100.10 0.500.20 0 10? details of "a" part "a" 1.50 .059 0.127 .005 1 pin index 0.10(.004) m 0.13(.005) 1994 fujitsu limited f64018s-1c-2 c 64-pin plastic qfp dimensions in mm (inches) lead pitch package width length lead shape sealing method 0.65 mm 12 12 mm gull-wing plastic mold 64-pin plastic qfp (fpt-64p-m09) (mounted height )
37 1.6 package dimensions n mqp-64c-p01 package dimension figure 1.6-3 mqp-64c-p01 package dimensions 64-pin ceramic mqfp (mqp-64c-p01) (mqp-64c-p01) +0.40 C0.20 +.016 C.008 +0.40 C0.20 +.016 C.008 1.20 .047 12.00(.472)typ (.039.010) 1.000.25 typ 18.00(.709) (.039.010) 1.000.25 (.016.004) 0.400.10 1.20 .047 (.016.004) 0.400.10 max 10.82(.426) (.006.002) 0.150.05 0.50(.020)typ 11.68(.460)typ 9.48(.373)typ 7.62(.300)typ 0.30(.012)typ (.050.005) 1.270.13 (.713.008) 18.120.20 typ 14.22(.560) typ 12.02(.473) typ 10.16(.400) typ 24.70(.972) (.878.013) 22.300.33 (.050.005) 1.270.13 typ 0.30(.012) index area 18.70(.736)typ (.642.013) 16.300.33 (.613.008) 15.580.20 1994 fujitsu limited m64004sc-1-3 c lead pitch lead shape motherboard material mounted socket material 1.00 mm straight ceramic plastic dimension in mm (inches) hes)
38 chapter 1 overview 1.7 i/o pins and pin functions table 1.7-1 "pin description" lists the mb89980 series i/o pins and their functions. table 1.7-2 "i/o circuit type" lists the i/o circuit types. the letter in the "i/o circuit type" column in table 1.7-1 "pin description" refers to the letter in the "type" column table 1.7-2 "i/o circuit type". n i/o pins and pin functions table 1.7-1 pin description pin no. pin name i/o circuit type function lqfp* 1 qfp* 2 mqfp* 3 mb89983 mb89p985 mb89pv980 22 23 x0 a crystal or other resonator connector pins for the main clock. the external clock can be connected to x0. when this is done, be sure to leave x1 open. cr oscillation selectability in model with a mask rom only. 23 24 x1 20 21 mod0 c r c a hysteresis input type memory access mode setting pins connect directly to vss. 21 22 mod1 19 20 rst d reset i/o pin this pin is an n-ch open-drain output type with a pull-up resistor, and a hysteresis input type. "l" is output from this pin by an internal reset request (optional). the internal circuit is initialized by the input of "l". 14 to 15 15 to 16 p00/ int20 to p01/ int21 e f general-purpose i/o ports also serve as an external interrupt 2 input (wake-up function). external interrupt 2 input is hysteresis input. 25 to 30 26 to 31 p02/ int22 to p07/ int27 e f general-purpose i/o ports also serve as an external interrupt 2 input (wake-up function). external interrupt 2 input is hysteresis input.
39 1.7 i/o pins and pin functions 31 to 34 32 to 35 p10/ int10 to p13/ int13 e f general-purpose i/o ports also serve as input for external interrupt 1 input (wake-up function). external interrupt 1 input is hysteresis input. 35 to 38 36 to 39 p14 to p17 g h general-purpose i/o ports 39 40 p20/ec j k n-ch open-drain general-purpose i/o port also serve as the external clock input for the 8/16-bit timer/ counter. the peripheral is a hysteresis input. 40 41 p21 l m n-ch open-drain general-purpose i/o port 41 42 p22/to l m n-ch open-drain general-purpose i/o port also serves as an 8/16-bit timer/ counter output. 42 43 p23 l m n-ch open-drain general-purpose i/o port 43 44 p24/rco l m n-ch open-drain general-purpose i/o port also serves as remote control output. 44 to 45 45 to 45 p25 to p26 l m n-ch open-drain general-purpose i/o port 46 47 p27/ pwm2 l m n-ch open-drain general-purpose i/o port also serves as the square wave or pwm wave output for the 8-bit pwm timer 2. 16 17 p30/ pwm1/ bz i general-purpose cmos output port also serves as the square wave or pwm wave output for the 8-bit pwm timer 1, or buzzer output. table 1.7-1 pin description pin no. pin name i/o circuit type function lqfp* 1 qfp* 2 mqfp* 3 mb89983 mb89p985 mb89pv980
40 chapter 1 overview 17 18 p31 r general-purpose cmos input port (hysteresis input type) x0a b crystal or other resonator connector pins for the subclock (subclock: 32.768 khz) the external clock can be connected to x0a. when this is done, be sure to leave x1a open. 18 19 p32 r general-purpose cmos input port (hysteresis input type) x1a b crystal or other resonator connector pins for the subclock (subclock: 32.768 khz) the external clock can be connected to x0a. when this is done, be sure to leave x1a open. 7 to 10 8 to 11 p50/an0 to p53/ an3 p q n-ch open-drain general-purpose output ports also serve as the analog input for the a/d converter. 57 to 64 58 to 64 and 1 p40/ seg0 to p47/ seg7 n/o s n-ch open-drain general-purpose output ports (high current type) also serve as an lcd controller/ driver segment output. switching between port and segment output is done by the mask option for mb89983 and by register for mb89p985/pv980. 1 to 2 2 to 3 p60/ seg8 to p61/ seg9 n/o s n-ch open-drain general-purpose output ports (high-current type) also serve as an lcd controller/ driver segment output. switching between port and segment output is done by the mask option for mb89983 and by register for mb89p9 85/pv980. table 1.7-1 pin description pin no. pin name i/o circuit type function lqfp* 1 qfp* 2 mqfp* 3 mb89983 mb89p985 mb89pv980
41 1.7 i/o pins and pin functions *1 : fpt-64p-m03 *2 : fpt-64p-m09 *3 : mqp-64c-p01 3 to 6 4 to 7 p62/ seg10 to p65/ seg13 n/o s n-ch open-drain general-purpose output ports also serve as an lcd controller/ driver segment output. switching between port and segment output is done by the mask option for mb89983 and by register for mb89p985/pv980. 54, 55 55, 56 p70/ com2, p71/ com3 t/o s n-ch open-drain general-purpose output ports also serve as an lcd controller/ driver common output. switching between port and common output is done by the mask option for mb89983 and by register for mb89p985/pv980. 52, 53 53, 54 com0, com1 o lcd controller/driver common output 47, 48, 50, 51 48, 49, 51, 52 v0 to v3 - - lcd driving power supply pins. 56 57 vcc - - power supply pin 24, 29 25, 50 vss - - power supply (gnd) pin 11 12 avcc - - a/d converter power supply pin 12 13 avr - - a/d converter reference voltage input pin 13 14 avss - - a/d converter power supply pin use this pin at the same voltage as vss. table 1.7-1 pin description pin no. pin name i/o circuit type function lqfp* 1 qfp* 2 mqfp* 3 mb89983 mb89p985 mb89pv980
42 chapter 1 overview table 1.7-2 i/o circuit type type circuit remarks a main clock (main clock crystal oscillator) ? at an oscillation feedback resistor of approximately 1 m w /5.0 v ? cr oscillation is selectable for mb89983 only b subclock (subclock crystal oscillator) ? at an oscillation feedback resistor of approximately 4.5 m w /5.0 v c ? hysteresis input ? at a pull-down resistor (p-ch) of approximately 50 k w /5.0 v d ? at an output pull-up resistor (p-ch) of approximately 50 k w /5.0 v ? hysteresis input e ? cmos output ? cmos input ? the peripheral is a hysteresis input type. ? pull-up resistor is approximately 50 k w / 5.0 v ? pull-up resistor is selected by mask option. x1 x0 n-ch p-ch p-ch n-ch x1a x0a n-ch p-ch p-ch n-ch n-ch p-ch n-ch r r p-ch n-ch port peripheral r p-ch
43 1.7 i/o pins and pin functions f ? cmos output ? cmos input ? the peripheral is a hysteresis input type. ? pull-up resistor is approximately 50 k w / 5.0 v ? pull-up resisitor is selected by pull-up control register g ? cmos output ? cmos input ? pull-up resistor is approximately 50 k w / 5.0 v ? pull-up resistor is selected by mask option. h ? cmos output ? cmos input ? pull-up resistor is approximately 50 k w / 5.0 v ? pull-up resisitor is selected by pull-up control register i ? cmos output table 1.7-2 i/o circuit type type circuit remarks p-ch n-ch r p-ch port peripheral pul l-up control registe p-ch n-ch por t r p-ch p-ch n-ch r p-ch port pull-up control register p-ch n-ch
44 chapter 1 overview j ? n-ch open-drain output ? cmos input ? the peripheral is a hysteresis input type. ? pull-up resistor is approximately 50 k w / 5.0 v ? pull-up resistor is selected by mask option. k ? n-ch open-drain output ? cmos input ? the peripheral is a hysteresis input type. l ? n-ch open-drain output ? cmos input ? p21, p26, and p27 are a heavy-current drive type. ? pull-up resistor is approximately 50 k w / 5.0 v ? pull-up resistor is selected by mask option. m ? n-ch open-drain output ? cmos input ? p21, p26, and p27 are a heavy-current drive type. n ? n-ch open-drain output ? pull-up resistor is approximately 50 k w / 5.0 v ? pull-up resistor is selected by mask option. table 1.7-2 i/o circuit type type circuit remarks peripheral por t n-ch r p-ch peripheral port n-ch port n-ch r p-ch port n-ch n-ch r p-ch
45 1.7 i/o pins and pin functions o ? lcd controller/driver common/segment output p ? n-ch open-drain output ? analog input (a/d converter) ? pull-up resistor is approximately 50 k w / 5.0 v ? pull-up resistor is selected by mask option. q ? n-ch open-drain output ? analog input (a/d converter) ? pull-up resistor is approximately 50 k w / 5.0 v ? pull-up resisitor is selected by pull-up control register r ? hysteresis input s ? n-ch open-drain output ? lcd controller/driver segment output t ? n-ch open-drain output table 1.7-2 i/o circuit type type circuit remarks n-ch p-ch p-ch n-ch n-ch p-ch analog input r p-ch n-ch r p-ch p-ch analog input pull-up control register n-ch n-ch p-ch p-ch n-ch n-ch
46 chapter 1 overview
47 chapter 2 handling devices this chapter describes points to note when using the general-purpose single-chip microcontroller. 2.1 "notes on handling devices"
48 chapter 2 handling devices 2.1 notes on handling devices this section lists points to note regarding the power supply voltage, pins, and other device handling aspects. n notes on handling devices m take great care not to exceed the maximum rated voltage (prevent latchup). latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- to high-voltage pins, or if voltage higher than the ratings is applied between v cc and v ss . when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. also, take care to prevent the analog power supply (av cc and avr) and analog input from exceeding the digital power supply (v cc ) when the analog system power supply is turned on and off. m stabilizing supply voltage is important. a rapid fluctuation of v cc power supply voltage could cause malfunctions, even if it occurs within the operation assurance range of the voltage. as stabilization guidelines, it is recommended to control power so that v cc ripple fluctuations (p-p value) will be less than 10% of the standard v cc value at the commercial frequency (50 to 60 hz) and the transient fluctuation rate will be less than 0.1 v/ms at the time of a momentary fluctuation such as when power is switched. m treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be connected to a pull- up or pull-down resistor. m treatment of n.c. pins be sure to leave (internally connected) n.c. pins open. m treatment of power supply pins on microcontroller with a/d or d/a converters connect to be av cc = davc = v cc and av ss = avr = v ss even if the a/d and d/a converters are not in use. m precautions when using an external clock even when an external clock is used, oscillation stabilization delay time is required for power-on reset (optional) and wake-up from stop mode. m treatment of two vss pins two vss pins should be connected together externally.
49 2.1 notes on handling devices m treatment of input port pins in standby mode to avoid current leakage, it is recommended to remain a known logic level of input port pins during the standby mode.
50 chapter 2 handling devices
51 chapter 3 cpu this chapter describes the functions and operation of the cpu. 3.1 "memory space" 3.2 "dedicated registers" 3.3 "general-purpose registers" 3.4 "interrupts" 3.5 "resets" 3.6 "clocks" 3.7 "standby modes (low-power consumption)" 3.8 "memory access mode"
52 chapter 3 cpu 3.1 memory space the microcontrollers of the mb89980 series offer a memory space of 64 kbytes. the memory space contains the i/o area, ram area, rom area, and external area. the memory space contains areas used for special purposes such as the general-purpose registers and vector table. n memory space structure m i/o area (addresses: 0000 h to 007f h ) ? control registers and data registers for the internal peripheral functions are located in this area. ? as the i/o area is allocated within the memory space, i/o can be accessed in the same way as memory. high-speed access using direct addressing is available. m ram area ? internal static ram is provided as an internal data area. ? the internal ram size differs between products. ? addresses between 80 h and ff h support high-speed access using direct addressing. ? addresses between 100 h and 1ff h can be used as the general-purpose register area (restrictions apply for some products). ? the contents of ram is indeterminate after a reset. m rom area ? internal rom is provided as an internal program area. ? the internal rom size differs between products. setting the memory access mode to external rom mode enables internal rom to be disconnected and set as an external area. ? addresses between ffc0 h and ffff h are used for the vector table, etc.
53 3.1 memory space n memory map figure 3.1-1 memory map i/o ram rom mb89983 0000 h 0080 h 0100 h 0180 h ffc0 h ffff h e000 h access prohibited registers vector table i/o ram rom mb89p985 0000 h 0080 h 0100 h 0280 h ffc0 h ffff h c000 h access prohibited registers (reset, interrupt, vector call instruction) 0200 h i/o ram rom mb89pv980 0000 h 0080 h 0100 h 0280 h ffc0 h ffff h 8000 h access prohibited * registers 0200 h * : in-circuit emulator (ice) tools can be used to access memory range 0280 h ~ 7ffff
54 chapter 3 cpu 3.1.1 special areas in addition to the i/o area, the special purpose areas in the memory space include the general-purpose register area and the vector table area. n general-purpose register areas (addresses: 0100 h to 01ff h ) ? provides auxiliary registers for 8-bit arithmetic operation and transfer instructions. ? allocated to a region of the ram area. can also be used as normal ram. ? using the area as general-purpose registers enables high-speed access by general-purpose register addressing using short instructions. table 3.1-1 "general-purpose register areas" lists the areas in each device that can be used for general-purpose registers. reference: see section 3.2.2 "register bank pointer (rp)" and section 3.3 "general-purpose registers" for details. n vector table area (addresses: ffc0 h to ffff h ) ? used as the vector table for the vector call instruction, interrupts, and resets. ? the vector table is allocated at the top of the rom area. the start address of the corresponding processing routine is set as data at each vector table address. table 3.1-2 "vector table" lists the vector table addresses referenced by the vector call instruction, interrupts, and resets. reference: see section 3.4 "interrupts" section 3.5 "resets" and "(6) callv #vct" in appendix b.3 "special instructions" for details. table 3.1-1 general-purpose register areas cpu mb89983 mb89p985 mb89pv980 number of banks 16 32 32 address range 0100 h to 017f h 0100 h to 01ff h 0100 h to 01ff h
55 3.1 memory space table 3.1-2 vector table vector call instruction vector table address interrupts vector table address upper lower upper lower callv #0 ffc0 h ffc1 h irqb ffe4 h ffe5 h callv #1 ffc2 h ffc3 h irqa ffe6 h ffe7 h callv #2 ffc4 h ffc5 h irq9 ffe8 h ffe9 h callv #3 ffc6 h ffc7 h irq8 ffea h ffeb h callv #4 ffc8 h ffc9 h irq7 ffec h ffed h callv #5 ffca h ffcb h irq6 ffee h ffef h callv #6 ffcc h ffcd h irq5 fff0 h fff1 h callv #7 ffce h ffcf h irq4 fff2 h fff3 h irq3 fff4 h fff5 h irq2 fff6 h fff7 h irq1 fff8 h fff9 h irq0 fffa h fffb h more data -* fffd h reset vector fffe h ffff h fffc h is not available. (set ff h .)
56 chapter 3 cpu 3.1.2 storing 16-bit data in memory for 16-bit data and the stack, store the upper data in the lower memory address value. n storing 16-bit data in ram when writing 16-bit data to memory, store the upper byte at the lower address and the lower byte at the next address. handle reading of 16-bit data in the same way. figure 3.1-2 "storing 16-bit data in memory" shows how 16-bit data is stored in memory. figure 3.1-2 storing 16-bit data in memory n storing 16-bit operands the byte order applies when specifying a 16-bit operand in an instruction. store the upper byte at the address following the operation code (instruction) and the lower byte at the next address. the byte ordering applies to both 16-bit immediate data and operands that specify a memory address. figure 3.1-3 "byte order of 16-bit data in an instruction" shows how 16-bit data is stored in an instruction. figure 3.1-3 byte order of 16-bit data in an instruction n storing 16-bit data on stack the same byte order applies when saving 16-bit register data on the stack during an interrupt or similar. the upper byte is stored in the lower address. before execution 1 2 3 4 h 0080 h 0081 h 0082 h 0083 h a 0080 h 0081 h 0082 h 0083 h after execution 1 2 3 4 h 12 h 34 h memory memory movw 0081h,a a . . . [example] mov a,5678h ; extended address movw a,#1234h ; 16-bit immediate data x x x 0 h xx xx x x x 2 h 60 56 78 ; extended address x x x 5 h e4 12 34 ; 16-bit immediate data x x x 8 h xx . . . after assembly
57 3.2 dedicated registers 3.2 dedicated registers the dedicated registers in the cpu consist of the program counter (pc), two arithmetic operation registers (a and t), three address pointers (ix, ep, and sp), and the program status (ps). all registers are 16 bits. n dedicated register configuration the dedicated registers in the cpu consist of seven 16-bit registers. some of these registers are also able to be used as 8-bit registers, using the lower 8 bits only. figure 3.2-1 "dedicated register configuration" shows the structure of the dedicated registers. figure 3.2-1 dedicated register configuration n dedicated register functions m program counter (pc) the program counter is a 16-bit counter that indicates the memory address of the instruction currently being executed by the cpu. instruction execution, interrupts, resets, and similar update the contents of the program counter. the initial value during a reset is the read address of the mode data (fffd h ). m accumulator (a) the accumulator is a 16-bit arithmetic operation register. the accumulator is used to perform arithmetic operations and data transfers with data in memory or in other registers such as the temporary accumulator (t). the content of the accumulator can be treated as either word (16- bit) or byte (8-bit) data. only the lower 8 bits (al) of the accumulator are used for byte arithmetic operations or transfers. in this case, the upper 8 bits (ah) remain unchanged. the content of the accumulator after a reset is indeterminate. pc a t ix ep sp rp ccr 16 bits ps initial value indeterminate indeterminate indeterminate indeterminate indeterminate fffd h : program counter a register for indicating the current instruction storage positions : accumulator a temporary register for storing arithmetic operations or transfer instructions : te mporary accumulator a register which performs arithmetic operations with the accumulator : index register a register for indicating an index address : extra pointer a pointer for indicating a memory address : stack pointer a register for indicating the current stack location : program status a register for storing a register bank pointer and condition code i-flag = "0", il0, il1 = "11" other bits are indeterminate
58 chapter 3 cpu m temporary accumulator (t) the temporary accumulator is an auxiliary 16-bit arithmetic operation register used to perform arithmetic operations with the data in the accumulator (a). the content of the temporary accumulator is treated as word data (16-bit) for word-length arithmetic operations with the accumulator and as byte data (8-bit) for byte-length arithmetic operations. for byte-length arithmetic operations, only the lower 8 bits of the temporary accumulator (tl) are used and the upper 8 bits (th) are not used. executing a transfer instruction to transfer data to the accumulator (a) automatically transfer the previous content of the accumulator to the temporary accumulator. in this case also, a byte transfer leaves the upper 8 bits of the temporary accumulator (th) unchanged. the content of the temporary accumulator after a reset is indeterminate. m index register (ix) the index register is a 16-bit register used to hold the index address. the index register is used in conjunction with a single byte offset value (-128 to +127). adding the sign-extended offset value to the index address generates the memory address for data access. the content of the index register after a reset is indeterminate. m extra pointer (ep) the extra pointer is a 16-bit register used to hold a memory address for data access. the content of the extra pointer after a reset is indeterminate. m stack pointer (sp) the stack pointer is a 16-bit register used to hold the address referenced during operations such as interrupts, subroutine calls, and the stack save and restore instructions. the value of the stack pointer during program execution is the address of the most recently saved data on the stack. the content of the stack pointer after a reset is indeterminate. m program status (ps) the program status is a 16-bit control register. the upper 8 bits contain the register bank pointer (rp) which points to the address of the current general-purpose register bank. the lower 8 bits contain the condition code register (ccr) which contains flags indicating the current cpu status. the two 8-bit registers which form the program status cannot be accessed independently (the program status can only be accessed by the movw a,ps and movw ps,a instructions). reference: refer to the f2mc-8l mb89600 series programming manual for details on using the dedicated registers.
59 3.2 dedicated registers 3.2.1 condition code register (ccr) the condition code register (ccr) located in the lower 8 bits of the program status (ps) consists of the c, v, z, n, and h bits indicating the results of arithmetic operations and the contents of transfer data, and the i, il1, and il0 bits for control whether or not the cpu accepts interrupt requests. n structure of condition code register (ccr) figure 3.2-2 structure of condition code register n arithmetic operation result bits m half-carry flag (h) set when a carry from bit 3 to bit 4 or a borrow from bit 4 to bit 3 occurs as a result of an arithmetic operation. cleared otherwise. as this flag is for the decimal adjustment instructions, do not use this flag in cases other than addition or subtraction. m negative flag (n) set if the most significant bit (msb) is set to 1 as a result of an arithmetic operation. cleared when the bit is set to 0. m zero flag (z) set when an arithmetic operation results in 0. cleared otherwise. m overflow flag (v) set if the complement on 2 overflows as a result of an arithmetic operation. reset if the overflow does not occur. half-carry flag interrupt enable flag interrupt level bits negative flag zero flag overflow flag carry flag bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r4 r3 r2 r1 r0 h i il1il0n z v c ccr initial value x011xxxx b rp ccr ps x: indeterminate
60 chapter 3 cpu m carry flag (c) set when a carry from bit 7 or borrow to bit 7 occurs as a result of an arithmetic operation. cleared otherwise. set to the shift-out value in case of a shift instruction. figure 3.2-3 "change of carry flag by shift instruction" shows the change of the carry flag by a shift instruction. figure 3.2-3 change of carry flag by shift instruction check: the condition code register is part of the program status (ps) and cannot be accessed independently. note: in practice, the flag bits are rarely fetched and used directly. instead, the bits are used indirectly by instructions such as branch instructions (such as bnz) or the decimal adjustment instructions (daa, das). the content of the flags after a reset is indeterminate. n interrupt acceptance control bit m interrupt enable flag (i) interrupt is enabled when this flag is set to "1"and the cpu accepts interrupt. interrupt is prohibited when this flag is set to "0" and the cpu does not accept interrupt. the initial value after a reset is "0". normal practice is to set the flag to "1" by the seti instruction and clear to "0" by the clri instruction. m interrupt level bits (il1, il0) these bits indicate the level of the interrupt currently being accepted by the cpu. the value is compared with the interrupt level setting registers (ilr1 to ilr3) which have a setting for each peripheral function interrupt request (irq0 to irqb). given that the interrupt enable flag is enabled (i = "1"), the cpu only performs interrupt processing for interrupt requests with an interrupt level value that is less than the value of these bits. table 3.2-1 "interrupt level" lists the interrupt level priorities. the initial value after a reset is "11". c bit 7 bit 0 bit 7 bit 0 ? left shift (rolc) ? right shift (rorc) c
61 3.2 dedicated registers note: the interrupt level bits (il1, il0) are normally "11" when the cpu is not processing an interrupt (during main program execution). reference: see section 3.4 "interrupts" for details on interrupts. table 3.2-1 interrupt level il1 il0 interrupt level high-low 00 1 high 01 10 2 1 1 3 low (no interrupt)
62 chapter 3 cpu 3.2.2 register bank pointer (rp) the register bank pointer (rp) located in the upper 8 bits of the program status (ps) indicates the address of the general-purpose register bank currently in use. the rp is converted to form the actual address in general-purpose register addressing. n structure of register bank pointer (rp) figure 3.2-4 "structure of register bank pointer" shows the structure of the register bank pointer. figure 3.2-4 structure of register bank pointer the register bank pointer indicates the address of the register bank currently in use. figure 3.2- 5 "rule for conversion of actual addresses of general-purpose register area" shows the relationship between the pointer contents and the actual address is based on the conversion rule. figure 3.2-5 rule for conversion of actual addresses of general-purpose register area the register bank pointer points to the memory block (register bank) in the ram area that is used for general-purpose registers. a total of 32 register banks are available. a register bank is specified by setting a value between 0 and 31 in the upper 5 bits of the register bank pointer. each register bank contains eight 8-bit general-purpose registers. registers are specified by the lower 3 bits of the operation codes. using the register bank pointer, the addresses 0100 h to 01ff h can be used as the general- purpose register area. however, the available area is limited on some products if internal ram only is used. the initial value after a reset is indeterminate. check: the register bank pointer is part of the program status (ps) and cannot be accessed independently. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r4 r3 r2 r1 r0 h i il1il0n z v c rp initial value xxxxxxxx b rp ccr ps x: indeterminat e a15 a14 a13 a12 a10 a11 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 "0" "0" "0" "0" "0" "0" "0" "1" r4 r3 r2 r1 r0 b2 b1 b0 upper bits of rp lower operation codes generated addresses
63 3.3 general-purpose registers 3.3 general-purpose registers the general-purpose registers are a memory block made up of banks, with 8 8-bit registers per bank. the register bank pointer (rp) is used to specify the register bank. the function permits the use of up to 32 banks, but the number of banks that can actually be used depends on how much ram the device has. register banks are valid for interrupt processing, vector call processing, and subroutine calls. n structure of general-purpose registers ? the general-purpose registers are 8 bits and located in the register banks of the general- purpose register area (in ram). ? one bank contains eight registers (r0 to r7) and up to a total of 32 banks. however, the number of banks available for general-purpose registers is limited on some products if internal ram only is used. ? the register bank currently in use is specified by the register bank pointer (rp). the lower three bits of the operation code specify general-purpose register 0 (r0) to general-purpose register 7 (r7). figure 3.3-1 "register bank structure" shows the register bank structure.
64 chapter 3 cpu figure 3.3-1 register bank structure reference: see section 3.1.1 "special areas" for the general-purpose register area available for each product. lower 3 bits of the operation code *: the top address of a register bank = 0100 h + 8 (upper 5 bits of rp) r0 r1 r2 r3 r4 r5 r6 r7 r0 r7 r0 r7 : : : : : 000 001 010 011 100 101 110 111 000 111 000 111 100 h * 108 h * 1ff h 1f8 h * : : : : : bank 0 (rp="00000--- b ") bank 1 (rp="00001--- b ") bank 31 (rp="11111--- b ") bank 2 to bank 30 32 banks (ram area) the number of banks is limited on available ram size.
65 3.3 general-purpose registers n features of general-purpose registers general-purpose registers have the following features: ? ram can be accessed at high-speed using short instructions (general-purpose register addressing). ? registers are grouped in blocks in the form of register banks. this simplifies the process of saving register contents and dividing registers by function. dedicated register banks can be permanently assigned for each interrupt processing or vector call (callv #0 to #7) processing routine by general-purpose register. for example, register bank 4 interrupt 2. for example, a particular interrupt processing routine only uses a particular register bank which cannot be written to unintentionally by other routines. the interrupt processing routine only needs to specify its dedicated register bank at the start of the routine to effectively save the general-purpose registers in use prior to the interrupt. therefore, saving the general-purpose registers to the stack or other memory location is not necessary. this allows high-speed interrupt handling while maintaining simplicity. also, as an alternative to saving general-purpose registers in subroutine calls, register banks can be used to create reentrant programs (programs that do not use fixed addresses and can be entered more than once) usually made by the index register (ix). check: if an interrupt processing routine changes the register bank pointer (rp), ensure that the program does not also change the interrupt level bits in the condition code register (ccr: il1, il0) when specifying the register bank.
66 chapter 3 cpu 3.4 interrupts the mb89980 series has 12 interrupt request input corresponding to peripheral functions. an interrupt level can be set independently. if an interrupt request output is enabled in the peripheral function, an interrupt request from a peripheral function is compared with the interrupt level in the interrupt controller. the cpu performs interrupt operation according to how the interrupt is accepted. the cpu wakes up from standby modes, and returns to the interrupt or normal operation. n interrupt requests from peripheral functions table 3.4-1 "interrupt request and interrupt vector" lists the interrupt requests corresponding to the peripheral functions. on acceptance of an interrupt, execution branches to the interrupt processing routine. the contents of interrupt the vector table address corresponding to the interrupt request specifies the branch destination address for the interrupt processing routine. an interrupt processing level can be for each interrupt request in the interrupt level setting registers (ilr1, ilr2, ilr3). three levels are available. if an interrupt request with the same or lower level occurs during execution of an interrupt processing routine, the letter interrupt is not normally processed until the current interrupt processing routine completes. if interrupt request set the same level occur simultaneously, the highest priority is irq0. table 3.4-1 interrupt request and interrupt vector interrupt request vector table address bit names of the interrupt level setting register simultaneously- generated same- level irq priority upper lower irq0 (external interrupt 1-1) fffa h fffb h l01, l00 high irq1 (external interrupt 1-2) fff8 h fff9 h l11, l10 irq2 (external interrupt 1-3) fff6 h fff7 h l21, l20 irq3 (external interrupt 1-4) fff4 h fff5 h l31, l30 irq4 (external interrupt 2) fff2 h fff3 h l41, l40 irq5 (8/16-bit timer/counter) fff0 h fff1 h l51, l50 irq6 (vacancy) ffee h ffef h l61, l60 irq7 (timebase timer) ffec h ffed h l71, l70 irq8 (watch prescaler) ffea h ffeb h l81, l80 irq9 (pwm timer 1) ffe8 h ffe9 h l91, l90 irqa (pwm timer 2) ffe6 h ffe7 h la1,la0 irqb (a/d converter) ffe4 h ffe5 h lb1, lb0 low
67 3.4 interrupts 3.4.1 interrupt level setting registers (ilr1, ilr2, ilr3) the interrupt level setting registers (ilr1, ilr2, ilr3) together contain 12 blocks of 2- bit data, with each data corresponding to an interrupt request from a peripheral function. the interrupt level for each interrupt is set in that interrupts corresponding 2-bit data (interrupt level setting bits). n structure of interrupt level setting registers (ilr1, ilr2, ilr3) figure 3.4-1 structure of interrupt level setting registers two bits of the interrupt level setting registers are allocated to each interrupt request. the value of the interrupt level setting bits in these registers sets the interrupt priority (interrupt levels 1 to 3). the interrupt level setting bits are compared with the interrupt level bits in the condition code register (ccr: il1, il0). the cpu does not accept interrupt requests set to interrupt level 3. table 3.4-2 "interrupt level setting bit and interrupt level" shows the relationship between the interrupt level setting bits and the interrupt levels. register address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value ilr1 007c h l31 l30 l21 l20 l11 l10 l01 l00 11111111 b wwwwwwww ilr2 007d h l71 l70 l61 l60 l51 l50 l41 l40 11111111 b wwwwwwww ilr3 007e h lb1 lb0 la1 la0 l91 l90 l81 l80 11111111 b wwwwwwww w: write-only table 3.4-2 interrupt level setting bit and interrupt level l01 to lb1 l00 to lb0 request interrupt level high-low 00 1 high low (no interrupt) 01 10 2 11 3
68 chapter 3 cpu note: the interrupt level bits in the condition code register (ccr: il1, il0) are normally "11" during main program execution. check: as the irl1, ilr2, and ilr3 registers are write-only, the bit manipulation instructions cannot be used.
69 3.4 interrupts 3.4.2 interrupt processing the interrupt controller transmits the interrupt level to the cpu when an interrupt request is generated by a peripheral function. if the cpu is able to receive the interrupt, the cpu temporarily halts the currently executing program and executes the interrupt processing routine. n interrupt processing the procedure for interrupt operation is performed in the following order: interrupt source generated at peripheral function, set the interrupt request flag bit (request ff), discriminate the interrupt request enable bit (enable ff), the interrupt level (ilr1, ilr2, ilr3 and ccr: il1, il0), simultaneously generated interrupt requests with the same level, then check the interrupt enable flag (ccr: i). figure 3.4-2 "interrupt processing" shows the interrupt processing.
70 chapter 3 cpu figure 3.4-2 interrupt processing start initialize peripheral is an interrupt request present at the peripheral? is interrupt request output enabled for the peripheral? check the interrupt priority level and transfer the level to the cp u compare the level with the il bits in ps is the level higher than il? i-flag = 1? interrupt processing routine clear interrupt request execute interrupt processing reti restore pc and ps save pc and ps to the stack pc interrupt vector update il in ps internal bus register file ipla ir ps i il condition code register (ccr) check comparator wake-up from f 2 mc-8lcpu ram (5) (7) (6) (3) (4) enable ff request ff and peripherals level comparator interrupt controller (1) (3) (4) (5) (7) (6) yes yes yes yes no no no no stop mode wake-up from sleep mode main program execution (2) exit watch mode (1) after a reset, all interrupt requests are disabled. initialize the peripheral functions that are to generate interrupts in the peripheral function initialization program, set the interrupt levels in the appropriate interrupt level setting registers (ilr1, ilr2, ilr3), and start peripheral function. the interrupt level can be set to 1, 2 or 3. level 1 is the highest priority, followed by level 2. setting level 3 disables the interrupt for that peripheral function. (2) execute the main program (for multiple interrupts, execute the interrupt processing routine).
71 3.4 interrupts check: as the interrupt request flag bit of a peripheral function is not cleared automatically when an interrupt request is received, the bit must be cleared by the program (normally, by writing "0" to the interrupt request flag bit) at interrupt processing routine. reference: an interrupt wakes up the cpu from standby mode (low-power consumption). see section 3.7 "standby modes (low-power consumption)" for details. note: if the interrupt request flag bit is cleared at the top of the interrupt processing routine, the peripheral function that has generated the interrupt becomes able to generate another interrupt during execution of the interrupt processing routine (resetting the interrupt request flag bit). however, the interrupts are not normally accepted until the current processing routine completes. (3) the interrupt request flag bit (request ff) for a peripheral function is set to "1" when the peripheral function generates an interrupt source. if the interrupt request enable bit for the peripheral function is set to enable? (enable ff = "1"), the peripheral function outputs the interrupt request to the interrupt controller. (4) the interrupt controller continuously monitors for interrupt requests from the peripheral functions and passes the interrupt level of the current interrupt request with the highest interrupt level to the cpu. the interrupt controller also evaluates the priority order if requests with the same level are present simultaneously. (5) if the interrupt level received by the cpu has a higher priority (a lower level value) than the level set in the interrupt level bits in the condition code register (ccr: il1, il0), the cpu checks the interrupt enable flag (ccr: i) and receives the interrupt if interrupts are enabled (ccr: i = "1"). (6) the cpu saves the contents of the program counter (pc) and program status (ps) on the stack, reads the top address of the interrupt processing routine from the interrupt vector table for the interrupt, updates the interrupt level bits in the condition code register (ccr: il1, il0) with the received interrupt level, and starts execution of the interrupt processing routine. (7) finally, on execution of the reti instruction, the cpu restores the program counter (pc) and program status (ps) values saved on the stack and resumes execution from the instruction following the last instruction executed before the interrupt.
72 chapter 3 cpu 3.4.3 multiple interrupts multiple interrupts can be performed by setting different interrupt levels to the interrupt level setting register for two or more interrupt requests from peripheral functions. n multiple interrupts if the interrupt request having the higher interrupt levels occurs during the interrupt processing routines, the cpu halts the current interrupt process and switches to accept the interrupt with the higher priority. interrupt levels can be set in the range 1 to 3. however, the cpu does not accept interrupt requests set to interrupt level 3. m example of multiple interrupts as an example of multiple interrupt processing, assume that an external interrupt has a higher priority than the timer interrupt. the timer interrupt is set to level 2 and the external interrupt is set to level 1. figure 3.4-3 "example of multiple interrupts" shows the processing when the external interrupt occurs during execution of timer interrupt processing. figure 3.4-3 example of multiple interrupts ? during execution of timer interrupt processing, the interrupt level bits in the condition code register (ccr:il1, il0) are automatically set to the same value as the interrupt level setting register (ilr1, ilr2, ilr3) corresponding to the timer interrupt (level 2 in this example). if the interrupt request set to higher interrupt level (level 1 in this example) occurs at this time, the interrupt processing has priority. ? to temporarily disable multiple interrupts during the timer interrupt, the interrupt enable flag in the condition code register is set to "interrupts disabled" (ccr: i = "0") or the interrupt level bits (il1, il0) set to "00". ? on execution of the interrupt return instruction (reti) at the completion of interrupt processing, the cpu restores the program counter (pc) and program status (ps) values saved on the stack and resumes execution of the interrupted program. restoring the program status (ps) returns the condition code register (ccr) to the value prior to the interrupt. (4) (5) (6) (7) (1) (2) (3) (8) main program initialize peripheral timer interrupt occurs restart main program interrupt level 2 (ccr:il1, il0 = 10) timer interrupt processing external interrupt halt restart timer interrupt timer interrupt returns processing interrupt level 1 (ccr:il1, il0 = 01) external interrupt processing external interrupt processing external interrupt returns occurs
73 3.4 interrupts 3.4.4 interrupt processing time the total time from the generation of an interrupt request until control passes to the interrupt processing routine is the sum of the time required to complete execution of the current instruction and the interrupt handling time (the time required to prepare for interrupt processing). the maximum time for this process is 30 instruction cycles. n interrupt processing time when an interrupt request occurs, the time until the interrupt is accepted and the interrupt processing routine is executed includes the interrupt request sampling time and the interrupt handling time. m interrupt request sampling time whether or not an interrupt request has occurred is determined by sampling and testing for interrupt requests during the final cycle of each instruction. therefore, the cpu is unable to identify interrupt requests during execution of an instruction. the longest delay occurs when an interrupt request is generated immediately after starting execution of a divu instruction, which has the longest instruction cycles (21 instruction cycles). m interrupt handling time nine instruction cycles are required to perform the following preparation for interrupt processing after the cpu accepts an interrupt request: ? save the program counter (pc) and program status (ps). ? set the top address of the interrupt processing routine (the interrupt vector) in the pc. ? update the interrupt level bits (ps:ccr: il1, il0) in the program status (ps). figure 3.4-4 "interrupt processing time" shows the interrupt processing time. figure 3.4-4 interrupt processing time the total interrupt processing time of 21 + 9 = 30 instruction cycles is required if an interrupt request occurs immediately after starting execution of a divu instruction, which has the longest instruction cycles (21 instruction cycles). if, on the other hand, the program does not use the divu or mulu instructions, the maximum interrupt processing time is 6 + 9 = 15 instruction cycles. cpu operation interrupt waiting time execution of a standard instruction interrupt request sampling time interrupt request occurs interrupt handling interrupt handling time (9 instruction cycles) interrupt processing routine : final cycle of instruction. interrupt requests are sampled at this
74 chapter 3 cpu reference: the time of one instruction cycle changes with the clock mode and the main clock frequency as selected by the "speed-shift" (gear) function. see section 3.6 "clocks" for details.
75 3.4 interrupts 3.4.5 stack operation during interrupt processing this section describes the saving of the register contents to the stack and restore operation during interrupt processing. n stack operation at start of interrupt processing the cpu automatically saves the current contents of the program counter (pc) and program status (ps) to the stack when an interrupt is accepted. figure 3.4-5 "stack operation at start of interrupt processing" shows the stack operation at the start of interrupt processing. figure 3.4-5 stack operation at start of interrupt processing n stack operation at interrupt return on execution of the interrupt return instruction (reti) at the completion of interrupt processing, the cpu performs the opposite processing to interrupt initiation, restoring first the program status (ps) and then the program counter (pc) from the stack. this returns the ps and pc to their states immediately prior to the start of the interrupt. check: the cpu does not automatically save the accumulator (a) or temporary accumulator (t) contents to the stack. use the pushw and popw instructions to save and restore a and t contents to and from the stack. h h h h h h 027c h 027d h 027e h 027f h 0280 h 0281 h address memory 0870 h ps e000 h pc 0280 h sp immediately before interrupt 08 h 70 h e0 h 00 h h h 027c h 027d h 027e h 027f h 0280 h 0281 h address memory 027c h sp 0870 h ps e000 h pc immediately after interrupt ps
76 chapter 3 cpu 3.4.6 stack area for interrupt processing interrupt processing execution uses the stack area in ram. the contents of the stack pointer (sp) specifies the top address of the stack area. n stack area for interrupt processing the subroutine call instruction (call) and vector call instruction (callv) use the stack area to save and restore the program counter (pc). the stack area is also used by the pushw and popw instructions to temporarily save and restore registers. ? the stack area is located in ram along with the data area. ? initializing the stack pointer (sp) to the top address of ram and allocating data areas upwards from the bottom ram address is recommended. figure 3.4-6 "stack area for interrupt processing" shows the example of stack area setting. figure 3.4-6 stack area for interrupt processing note: the stack area is used in the downward direction starting from a high address by functions such as interrupts, subroutine calls, and the pushw instruction. instructions such as return instructions (reti, ret) and the popw instruction release stack area in the upward direction. take care when the stack address is decreased by multiple interrupts or subroutine calls that the stack does not overlap the general-purpose register area or areas containing other data. general- purpose registers i/o ram access rom 0000 h 0080 h 0100 h 0200 h ffff h recommended set value for sp data area stack area (when the top address of ram is 0280 h. ) prohibited 0280 h
77 3.5 resets 3.5 resets the mb89980 series supports the following four types of reset source: ? external reset ? software reset ? watchdog reset ? power-on reset (optional) at reset, main clock oscillation stabilization delay time may or may not occur by the operating mode and option settings. n reset source m external reset inputting an "l" level to the external reset pin (rst ) generates an external reset. returning the reset pin to the "h" level wakes up the cpu from the external reset. when power is turned on to products with power-on reset or for external resets in stop mode, the reset operation is performed after the oscillation stabilization delay time has passed and the cpu wakes up from the external reset. external resets on products without power-on reset do not wait for the oscillation stabilization delay time. the external reset pin can also function as a reset output pin (optional). m software reset writing "0" to the software reset bit in the standby control register (stbc: rst) generates a four-instruction cycle reset. the software reset does not wait for the oscillation stabilization delay time. m watchdog reset the watchdog reset generates a four-instruction cycle reset if data is not written to the watchdog timer control register (wdtc) within a fixed time after the watchdog timer starts. the watchdog reset does not wait for the oscillation stabilization delay time. table 3.5-1 reset source reset source reset conditions external reset set the external reset pin to the "l" level. software reset write "0" to the software reset bit in the standby control register (stbc: rst). watchdog reset watchdog timer overflow power-on reset power is turned on (only on products with a power-on reset).
78 chapter 3 cpu m power-on reset products can be set to with or without power-on reset (optional). on products with power-on reset, turning on the power generates a reset. the reset operation is performed after the oscillation stabilization delay time has passed. on products without power-on reset, an external reset circuit is required to generate a reset when the power is turned on. n main clock oscillation stabilization delay time and the reset source whether there will be an oscillation stabilization delay time depends on the operating mode when reset occurs, and the power-on reset option selected. following reset, operation always starts out in the normal main clock operating mode, regardless of the kind of reset it was, or the operating mode (the clock mode and standby mode) prior to reset. therefore, if reset occurs while the main clock oscillator is stopped or in a stabilization delay time, the system will be in a "main clock oscillation stabilization reset" state, and a clock stabilization period will be provided. if the device is set for no power-on reset, however, no main clock oscillation stabilization delay time is provided for power-on or external reset. in software or watchdog reset, if the reset occurs while the device is in main clock mode, no stabilization time is provided. if it occurs in the subclock mode, however, a stabilization time is provided since the main clock oscillation is stopped. table 3.5-2 "reset source and oscillation stabilization delay time" shows the relationships between the reset sources and the main clock oscillation stabilization delay time, and reset mode (mode fetch) operations. table 3.5-2 reset source and oscillation stabilization delay time reset source operating state reset operation and main clock oscillation stabilization delay time with power-on reset without power-on reset external reset* 1 at power on, during stop mode, or subclock mode after the main clock oscillation stabilization delay time, if the external reset is waked up, reset is operated.* 2 reset state is held until external reset is waked up; then the reset is operated. software and watchdog reset main clock mode after 4-instruction-cycle reset occurs, reset is operated.* 3 subclock mode reset is operated after the main clock oscillation stabilization delay time.* 2 power-on reset device enters main clock oscillation stabilization delay time at power on. reset is operated after delay time ends.* 2 an external circuit must be provided to hold external reset asserted at power on until main clock has had time to stabilize. *1: no oscillation stabilization delay time is required for external reset while main clock mode is operating. reset is operated after external reset is waked up. *2: if the reset output option is selected, "l" is output at rst pin during the main clock oscillation stabilization delay time. *3: if the reset output option is selected, "l" level is output at rst pin during 4-instruction-cycle.
79 3.5 resets 3.5.1 external reset pin inputting an "l" level to the external reset pin generates a reset. if products are set to with the reset output (optional), the pin outputs an "l" level depending on internal reset sources. n block diagram of external reset pin the external reset pin (rst ) on products with the reset output is a hysteresis input type and n- ch open-drain output type with a pull-up resistor. the external reset pin on products without a reset output option is only for the reset input. figure 3.5-1 "block diagram of external reset pin" shows the block diagram of the external reset pin. figure 3.5-1 block diagram of external reset pin n external reset pin functions inputting an "l" level to the external reset pin (rst ) generates an internal reset signal. on products with the reset output, the pin outputs an "l" level depending on internal reset sources or during the oscillation stabilization delay time due to an external reset. software reset, watchdog reset, and power-on reset are classed as internal reset sources. check: the external reset input accepts asynchronous with the internal clock. therefore, initialization of the internal circuit requires a clock. especially when an external clock is used, a clock is needed to be input at the reset. p-ch n-ch rst pin pull-up resistor approx. 50 k /5.0v option with reset output without reset output internal reset source input buffer internal reset signal
80 chapter 3 cpu 3.5.2 reset operation when the cpu wakes up from a reset, the cpu selects the read address of the mode data and reset vector according to the mode pin settings, then performs a mode fetch. the mode fetch is performed after the oscillation stabilization delay time has passed when power is turned on to a product with power-on reset, or on wake-up from subclock or stop mode by a reset. if reset occurs during a write to ram, the contents of the ram address cannot be assured. n overview of reset operation figure 3.5-2 reset operation flow diagram during reset mode fetch (reset operation) normal operation (run state) software reset watchdog reset no no no external reset input power-on reset selected? yes yes yes power-on, subclock wakes up from external fetch mode data fetch reset vector fetch the instruction code from the address indicated by the reset vector and begin execution. power-on reset (optional) main clock oscillation stabilization delay reset operation reset? yes in subclock mode? main clock oscillation stabilization delay reset state no or stop mode? state main clock oscillation stabilization delay reset state
81 3.5 resets n mode pins the mb89980 series devices are single-chip mode devices. the mode pins (mod1 and mod0) must be tied to v ss . the mode pin settings determine whether the mode data and reset vector are read from internal rom. do not change the mode pin settings, even after the reset has completed. n mode fetch when the cpu wakes up from a reset, the cpu reads the mode data and reset vector from internal rom. m mode data (address: fffd h ) always set the mode to "00 h " (single-chip mode). m reset vector (address: fffe h (upper), ffff h (lower)) contains the address where execution is to start after completion of the reset. the cpu starts executing instructions from the address contained in the reset vector. n oscillation stabilization delay reset state on products with power-on reset, the reset operation for a power-on reset or external reset in subclock or stop (main/sub) mode starts after the main clock oscillation stabilization delay time selected by the stabilization delay time option. if the cpu has not woken up from the external reset input when the delay time completes, the reset operation does not start until the cpu wakes up from external reset. as the oscillation stabilization delay time is also required when an external clock is used, a reset requires that the external clock is input. the main clock oscillation stabilization delay time is timed by the timebase timer. on products without power-on reset, the oscillation stabilization delay reset state is not used. therefore, for such products, hold the external reset pin (rst ) at the "l" level to disable the cpu operation until the source oscillation stabilizes. n effect of reset on ram contents the contents of ram are unchanged before and after a reset other than power-on reset. if an external reset is input close to a write timing, however, the contents of the write address cannot be assured. for this reason, all ram locations being used should be initialized following reset.
82 chapter 3 cpu 3.5.3 pin states during reset reset initialized the pin states. n pin states during reset when a reset source occurs, with a few exceptions, all i/o pins (peripheral pins) go to the high- impedance state and the mode data is read from internal rom (pins with a pull-up resistor (optional) go to the "h" level.) n pin states after reading mode data with a few exceptions, the i/o pins remain in the high-impedance state immediately after reading the mode data. (pins with a pull-up resistor (optional) go to the "h" level.) check: for devices connected to pins that change to high-impedance state when a reset source occurs take care that malfunction does not occur due to the change in the pin states. reference: see appendix e "mb89980 series pin states" for pin states at times other than a reset.
83 3.6 clocks 3.6 clocks the clock generator is provided with two oscillators. by connecting with external resonators, the two circuits generate the high speed main clock and low speed subclock source oscillators. alternatively, externally generated clock inputs can be used. clock controller controls the speed and supply of the dual-clock signals according to the clock and standby modes. as an option, a one-clock system can also be selected. n clock supply map oscillation of a clock and its supply to the cpu and peripheral circuit (peripheral functions) are controlled by the clock controller. as shown in the map, operating clocks fed to the cpu and peripheral circuits are affected by main clock/subclock switching (clock mode), main clock speed switching (speed-shift function), and standby modes (sleep/stop/watch). divide-by-n output derived from the free-run counter clocked by the peripheral circuit clock is supplied to the peripheral functions. divide-by-n outputs from the timebase timer and watch prescaler are also supplied to the peripheral functions. these clocks, however, are not affected by the speed-shift function, etc. the timebase timer is clocked by the output of the main clock source oscillator after it is fed through a divide-by-n circuit, and the watch prescaler is clocked directly by the subclock oscillator. figure 3.6-1 "clock supply map" shows the clock supply map.
84 chapter 3 cpu figure 3.6-1 clock supply map lcd controller/driver 8/16-bit timer/counter peripheral functions continuous activation conversion and comparison 3 timebase timer supply to the cpu 1 t inst clock controller pin x1 pin x0 oscillation continuous activation watchdog timer 8-bit pwm timer 1 8-bit pwm timer 2 a/d converter main clock oscillator divide-by-two f ch oscillation stabilization delay controller pin ec to1 to2 watch prescaler free-run counter pin x1a pin x0a subclock oscillator 1 t inst divide-by-two f cl supply to peripheral circuit controller divide-by-four divide-by-eight divide-by-16 divide-by-64 sleep/stop/watch oscillation stabilization delay clock mode speed-shift function clock mode stop mode 3 3 *1, 3 *2 *1, 3 *1 *2 *2 *2 *4 *1 *1 *1: not affected by clock mode, speed-shift function, etc. *2: operating speed, etc., affected by clock mode or speed-shift function. *3: stops operating if its clock source (main or subclock oscillator) stops. *4: timebase timer output can be selected in continuous a/d conversion operating mode. in other modes, clock speed is affected by clock mode and speed-shift function. stop watch remote control output generator 4 *2 buzzer output 4 3 *1
85 3.6 clocks 3.6.1 clock generator enable and stop of the main clock and subclock oscillations are controlled by clock and stop modes. n clock generator m crystal or ceramic resonator connect as shown in figure 3.6-2 "connection example for a crystal or ceramic resonator". figure 3.6-2 connection example for a crystal or ceramic resonator note: a piezoelectric resonator (far series) that contains the external capacitors can also be used. see data sheet for details. m cr (main clock only) connect as shown in figure 3.6-3 "connection example for cr". external resistors and capacitors can only be used on devices with mask rom. x0 x1 cc main clock cc x0a x1a oscillator subclock oscillator mb89980 series dual-clock option 32.768 khz x0 x1 cc main clock p31/x0a p32/x1a oscillator subclock oscillator mb89980 series one-clock option r can be used as port input
86 chapter 3 cpu figure 3.6-3 connection example for cr m external clock connect the external clock to the x0 pin and leave x1 pin open, as shown in figure 3.6-4 "connection example for external clock" to use an external subclock source, connect the external clock to the x0a pin and leave the x1a pin open. figure 3.6-4 connection example for external clock check: in the mb89980 series, you can select a single clock system as an option. if only the main clock were to be used without the single clock option, there would be no way to recover once the system goes into subclock mode. therefore, the single clock option must be selected in order to operate with one clock. to use cr instead of a main clock oscillator, the device you are using must have mask rom. for information on selecting mask rom, see the appendix c "mask options". x0 x1 main clock cc x0a x1a oscillator subclock oscillator mb89980 series dual-clock option 32.768 khz x0 x1 c main clock oscillator subclock oscillator mb89980 series one-clock option r r c r p31/x0a p32/x1a can be used as port input x0 x1 main clock x0a x1a oscillator subclock oscillator mb89980 series dual-clock option x0 x1 main clock oscillator subclock oscillator mb89980 series one-clock option open open open 32.768 khz p31/x0a p32/x1a can be used as port input
87 3.6 clocks 3.6.2 clock controller the clock controller contains the following seven blocks: ? main clock oscillator ? subclock oscillator ? system clock selector ? clock controller ? oscillation stabilization delay time selector ? system clock control register (sycc) ? standby control register (stbc) n block diagram of clock controller figure 3.6-5 "block diagram of clock controller" shows the block diagram of the clock controller.
88 chapter 3 cpu figure 3.6-5 block diagram of clock controller subclock control enable subclock oscillator pin state stop mode sleep mode watch mode clock for watch prescaler clock for divide-by-two divide-by-two main clock control system clock selector main clock oscillator enable prescaler divide-by-four divide-by-eight divide-by-16 divide-by-64 selector selector clock controller supply to supply to the peripheral circuits fr om timebase from watch prescaler oscillation stabilization delay time selector stop of supply to the cpu clock select timer f ch f cl : : subclock oscillation t inst : instruction cycle main clock oscillation the cpu timebase timer 2 2 /f ch 2 12 /f ch 2 16 /f ch 2 18 /f ch 2 15 /f cl 1 t inst 1 t inst sycc scm wt1 wt0 scs cs1 cs0 stbc stp slp spl rst tmd st bc 2 sycc
89 3.6 clocks m main clock oscillator the main clock oscillator is stopped in main-stop and subclock modes. m subclock oscillator the subclock oscillator is normally running except in sub-stop mode. it does not operate in "one- clock" option devices. m system clock selector the system clock selector selects one of five clocks: the subclock, or one of four divided clocks derived from the main clock master clock oscillator. m clock controller this circuit controls the supply of operating clocks to the cpu and peripheral circuits, selecting the clock based on the active mode: normal (run), or standby (sleep/stop/watch) mode. supply of the clock to the cpu is stopped until the clock supply stop signal in the oscillation stabilization delay time selector is released. m oscillation stabilization delay time selector this register selector selects a delay time from among four main clock oscillation stabilization times timed by the timebase timer and a subclock oscillation stabilization time timed by the watch prescaler, and outputs the time as the clock supply stop signal to the cpu based on the clock mode, standby mode and reset. m sycc register the sycc register is used to select the clock mode, the speed of the main clock, and the main clock oscillation stabilization delay time, and to check the status of these selections. m stbc register this register controls from normal operation (run) to the standby modes, sets the pin states in the stop or watch mode, and initiates software reset.
90 chapter 3 cpu 3.6.3 system clock control register (sycc) the system clock control register (sycc) controls main clock/subclock switching, main clock speed selection, and oscillation stabilization delay time selection. n structure of system clock control register (sycc) figure 3.6-6 structure of system clock control register (sycc) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0007 h scm wt1 wt0 scs cs1 cs0 x--mm100 b rr/wr/w r/w r/w r/w cs1 cs0 main clock speed select bit instruction cycle time (f ch = 4.2 mhz) 0 0 64/f ch (15.2s) 01 16/f ch (3.81 s) 10 8/f ch (1.90s) 11 4/f ch (0.95s) scs system clock select bit 0 selects subclock (32 khz) mode 1 selects main clock mode wt1 wt0 oscillation stabilization delay time select bit main clock oscillation stabilization delay time per selected timebase timer output (f ch = 4.2 mhz) 00 approx. 2 4 /f ch (approx. 0 ms) 01 approx. 2 12 /f ch (approx. 1.0 ms) 10 approx. 2 16 /f ch (approx. 15.6 ms) 11 approx. 2 18 /f ch (approx. 62.4 ms) scm system clock monitor bit 0 subclock (main clock stopped or in oscillation stabilization delay time) 1 main clock r/w : readable and writable r : read-only : unused bit x : indeterminate m : per option selection : initial value f ch : main clock oscillation
91 3.6 clocks table 3.6-1 system clock control register (sycc) bits bit function bit 7 scm: system clock monitor bit ? indicates the current clock mode (operating clock). ? "0" indicates subclock mode (main clock is stopped or in the oscillation stabilization delay time to go to main clock mode). ? "0" indicates main clock mode. note: this is a read-only bit. writing to it has no effect. bit 6 bit 5 unused bits ? the read value is indeterminate. ? writing to these bits has no effect on operation. bit 4 bit 3 wt1, wt0: oscillation stabilization delay time select bits ? select main clock oscillation stabilization delay time. ? selected wait time applies when going from subclock to main clock mode, or if external interrupt causes "wakeup" from main-stop mode (transition to normal (run) mode). ? initial value of these bits is an option selection. accordingly, when an oscillation stabilization delay time is provided at reset, the delay time will be as selected by the option. note: these bits should not be changed at the same time switching from subclock to main clock (scs = 1 --> 0). before changing the bits, first check the scm bit to verify that the device is not currently in the stabilization delay time. bit 2 scs: system clock select bit ? specifies the clock mode. ? writing "0" to this bit sets the cpu changing from main clock to subclock mode. ? writing "1" to this bit causes the device to go from subclock to main clock mode after the oscillation stabilization delay time set by wt1 and wt0 bits. note: if the single clock option is selected, this bit has no function. it should be set to "1". bit 1 bit 0 cs1, cs0: main clock speed select bits ? these bits select the clock speed for the main clock mode. ? four different speeds can be set for cpu and peripheral function operating clocks (speed-shift function). the clocks that clock the timebase timer and watch prescaler are not affected by these bits.
92 chapter 3 cpu n instruction cycle (tinst) instruction cycle (minimum execution time) can be selected as 1/4, 1/8, 1/16, or 1/64 of the main clock, or 1/2 of the subclock (32.768 khz clock) period. the selection is made by the system clock select bit (scs) and main clock speed select bits (cs1 and cs0) of the sycc register. with main clock mode, and the highest clock speed selected (sycc: scs = 1, cs1 = 11 b , cs0 = 11 b ), and with a main clock source oscillation (f ch ) of 4.2 mhz, the instruction cycle is 4/f ch = approximately 0.95 m s. with subclock mode selected (scs = 0), and with a subclock source oscillation (f cl ) of 32.768 khz, the instruction cycle is 2/f cl = approximately 61.0 m s.
93 3.6 clocks 3.6.4 clock modes the clock modes consists of main clock mode and subclock mode. in the main clock mode, the primary operating clock is provided by the main clock oscillator. the speed of the operating clock is selected by switching between one of four clocks obtained by dividing the output of the main clock oscillator (speed-shift function). in the subclock mode, the main clock oscillator is stopped, and operating clocks are provided solely by the subclock. n clock mode operating states table 3.6-2 clock mode operating states clock mode main clock speed sycc register (sycc: cs1, cs0) stand- by mode clock oscillator operating clocks for various sections non-reset event triggering exit from stanby main sub cpu time- base timer peri- pherals watch prescaler (1.1) run oscillate oscillate f ch /4 f ch /2 f ch /4 f cl irq sleep stop stop stop stop stop external interrupt main clock mode (1.0) run oscillate oscillate f ch /8 f ch /2 f ch /8 f cl irq sleep stop stop stop stop stop external interrupt (0.1) run oscillate oscillate f ch /16 f ch /2 f ch /16 f cl irq sleep stop stop stop stop stop external interrupt (0.0) run oscillate oscillate f ch /64 f ch /2 f ch /64 f cl irq sleep stop stop stop stop stop external interrupt sub- clock mode - run stop stop f cl stop* f cl f cl irq sleep stop stop stop stop stop external interrupt watch mode stop oscillate stop stop* stop f cl external or watch interrupt fast slow
94 chapter 3 cpu reference: see section 3.7 "standby modes" for a description of the standby modes." n speed-shift (main clock speed-switching) function one of four main clock frequencies can be selected by writing the appropriate values between "00b"and "11b" to main clock speed select bits of the system clock control register (sycc: cs1, cs0). the switch-selected clock signal provides the operating clock for the cpu and peripheral circuits. the timebase timer and watch prescaler, however, are not affected by the speed-shift (gear) function. a slower main clock speed reduces power consumption. n operation of main clock mode the main clock and the subclock oscillators both run in the "main-run" mode (the normal main clock operating mode). the watch prescaler runs on the subclock, but the cpu, timebase timer, and other peripheral circuits all use the main clock. when operating in main clock mode, the speed-shift function can be used to select a main clock speed. this selection affects all circuits that are clocked by the main clock except for the timebase timer. by specifying a standby mode, you can also go to "main-sleep,"or "main-stop" mode. when the device is reset, the system always starts out in "main-run" mode regardless of how the reset was initiated. (each operating mode exited by reset.) m changing from main clock mode to subclock mode writing "0" to the system clock select bit in the system clock control register (sycc:scs) changes the cpu from the main clock to subclock mode. you can determine which clock is currently being used by checking the system clock monitor bit of the same register (sycc: scm). check: if you go to subclock mode immediately after power on, write the software so as to provide a longer subclock oscillation stabilization delay time than that defined by the watch prescaler. n operation of subclock mode in the normal subclock operating mode ("sub-run" mode), the system runs on the subclock only. the main clock oscillator is stopped. using the low speed subclock reduces power consumption. other than the timebase timer, all functions operate the same in subclock mode as they do in main clock mode. if standby mode is specified while operating in subclock mode, the device goes to "sub-sleep," "sub-stop," or "watch" mode. m returning to main clock mode from subclock mode writing "1" to the system clock select bit in the system clock control register (sycc:scs) returns to main clock mode from subclock mode. operation from the main clock, however, will not start until after the main clock oscillation stabilization delay time has passed. one of four wait times can be selected by setting the f ch main clock source oscillation f cl subclock source oscillation *: since the timebase timer is derived from the main clock, it stops in subclock mode.
95 3.6 clocks oscillator stabilization delay time select bits of the system clock control register (sycc: wt1, wt0). check: do not change the oscillation stabilization delay time select bits (sycc: wt1, wt0) at the same time you switch from subclock to main clock mode (sycc: scs = 1), or during the oscillator stabilization delay time. always check the system clock monitor bit to verify that the main clock is the active operating clock (sycc: scm = 1) before changing these bits. if the device has the power-on reset option it always enters the oscillator stabilization delay time when the system is returned from subclock mode to main clock mode by reset. if the device does not have power-on reset option, there will be no delay time unless the reset was a software or watchdog reset.
96 chapter 3 cpu 3.6.5 oscillation stabilization delay time when the system transitions to main-run mode from a state in which the main clock is stopped (such as at power-on, and in main-stop and subclock modes, etc.), a delay time is required for oscillation to stabilize before operation starts. similarly, a subclock oscillation stabilization wait time is required when exiting the sub-stop mode, because the subclock oscillator is stopped in that mode. n oscillation stabilization delay time after starting, ceramic, crystal, and other resonators typically require the time between several milliseconds and several tens of milliseconds to stabilize at their fixed oscillation frequency. therefore, operation of the cpu and other functions is disabled when oscillation first starts and no clock signal is supplied to the cpu and peripheral functions until the oscillation stabilization delay time has passed and the oscillation has sufficiently stabilized. the time required for oscillation to stabilize depends on the resonator type (crystal, ceramic, etc.) connected to the clock generator. consequently, it is necessary to select an oscillation stabilization delay time that matches the type of oscillator being used. figure 3.6-7 "operation of oscillator after starting oscillation" shows the operation of an oscillator after starting oscillation. figure 3.6-7 operation of oscillator after starting oscillation n main clock oscillation stabilization delay time when first starting operation in main clock mode after a state in which the main clock oscillator is stopped, a delay time is required for oscillation to stabilize. this delay time starts when the timebase timer starts counting up from its cleared state, and ends when the count overflows at the specified bit. m oscillation stabilization delay time during operation a time length must be selected for the oscillation stabilization delay time when an external interrupt takes the system from main-stop mode back to main-run mode, or when going from subclock to main clock mode. one of four possible delay times can be selected, using the oscillator stabilization delay time select bits of the system clock control register (sycc: wt1, wt0). resonator oscillation time oscillation stabilization delay time normal operation (wake-up from stop mode or reset operation) oscillation starts oscillation stabilizes
97 3.6 clocks m oscillation stabilization delay time at reset the oscillation stabilization delay time at reset (the initial values of wt1 and wt0) is selected as an option setting. products with power-on reset require an oscillation stabilization delay time when exit from stop mode is triggered by resets in subclock mode (multiple), power-on reset, or external reset. products without power-on reset only require an oscillation stabilization delay time for watchdog reset or software reset during subclock mode. table 3.6-3 "main clock startup conditions vs. oscillation stabilization delay time" shows the relationships between the conditions in which main clock mode operation is started and oscillation stabilization delay time. n subclock oscillation stabilization delay time when an external interrupt returns the system from sub-stop (subclock oscillator stopped) to sub-run mode (thus starting the subclock oscillator), a set subclock oscillation stabilization delay time is provided. (this set delay time is equal to 2 15 /f cl , where f cl is the subclock oscillator frequency.) the subclock oscillation stabilization delay time is also entered at power-on. therefore, if you go to subclock mode after power on, you should insert a software delay, to provide a longer delay time before starting this transition than the subclock oscillation stabilization delay time alone. the subclock oscillation stabilization delay time starts when the watch prescaler starts counting up from the cleared state, and ends when it overflows. table 3.6-3 main clock startup conditions vs. oscillation stabilization delay time main clock mode startup conditions at power-on during subclock mode exit from main-stop transition from subclock to main clock mode (sycc: scs* 1 =1) external reset software reset and watchdog reset external reset external interrupt oscillation stabilization delay time selection option setting sycc: wt1, wt0 * 2 with power-on reset o oooo o no power-on reset x x o x o o o: oscillation stabilization delay time provided x: oscillation stabilization delay time not provided *1 system clock select bit of system clock control register *2 oscillation stabilization delay time select bits of system clock control register
98 chapter 3 cpu 3.7 standby modes (low-power consumption) the standby modes consist of sleep mode, stop mode, and watch mode. from both main and subclock clock modes, standby modes are changed to sleep mode, stop mode, or watch mode by setting the standby control register (stbc). from main clock mode, you can go only to sleep or stop mode, but from subclock mode you can go any of the three standby modes. standby mode reduces the power consumption by stopping the operation of the cpu and peripheral functions. this section describes the relationship between standby mode and clock mode, and the operation of various sections during standby. n standby modes watch mode reduce the power consumption by lowering the frequencies of the clocks that run the cpu and peripheral circuits. you can do this by switching from main clock to subclock mode, or by using the speed-shift function to select a lower main clock frequency. standby mode reduce the power consumption, however, by stopping the clock signal supply to the cpu via clock controller (sleep mode), by stopping the clock signal supply to the cpu and peripheral circuits (watch mode), or by stopping the source oscillator itself (stop mode). m main-sleep mode main-sleep mode stops the cpu and watchdog timer, but operate the peripheral functions except watch prescaler by the main clock. (certain functions can still run on the subclock.) m sub-sleep mode sub-sleep mode stops the main clock oscillator, cpu, watchdog timer, and timebase timer, but operate the peripheral functions on the subclock. m main-stop mode main-stop mode stops the cpu and peripheral functions. the main clock oscillator is stopped, but the subclock oscillator keeps running. everything is shut down except external interrupt servicing, watch prescaler counter operation, and some functions that operate from the subclock. m sub-stop mode sub-stop mode stops all chip functions except the external interrupt, and stops the main clock and subclock oscillations. m watch mode you can only go to watch mode from the subclock clock mode. all functions are shut down except the watch prescaler (watch interrupt), external interrupts, and some functions that operate from the subclock. even when the main clock is stopped, as it is in the main-stop a even when the main clock is stopped, as it is in the main-stop and watch modes, as long as the subclock oscillation is still operating, lcd controller/drivers will still operate. see chapter 14 "lcd controller/driver" and the clock supply map provided in section 3.6 "clocks" for details.
99 3.7 standby modes (low-power consumption) 3.7.1 operating states in standby modes this section describes the operating states of the cpu and peripheral functions in standby modes. n operating states during standby modes table 3.7-1 operating states of the cpu and peripheral functions in standby modes function main clock mode subclock mode run sleep stop run sleep stop watch main clock operating operating stop stop stop stop stop subclock operating operating operating operating operating stop operating c p u instructions operating stop stop operating stop stop stop rom operating hold hold operating hold hold hold ram p e r i p h e r a l f u n c t i o n s i/o ports operating hold hold operating hold hold hold watch prescaler operating operating operating* 1 operating operating stop operating timebase timer operating operating stop stop stop stop stop 8/16-bit timer/ counter operating operating stop operating operating stop stop remote control output frequency generator operating operating stop operating operating stop stop lcd controller- driver operating operating operating* 2 operating* 2 operating* 2 stop operating* 2 8-bit pwm timers operating operating stop operating operating stop stop a/d converter operating operating stop operating operating stop stop external interrupts 1 and 2 operating operating operating operating operating operating operating buzzer output operating operating operating* 3 operating* 3 operating* 3 stop operating* 3 watchdog timer operating stop stop operating* 3 stop stop stop
100 chapter 3 cpu m pin states in standby mode almost all i/o pins will either keep the state they were placed in by the pin state control bit of the standby control register (stbc: spl) just prior to going to the stop or watch mode, or will go to the high impedance state. this is true regardless of the clock mode. reference: see appendix e "mb89980 series pin states." for pin states in a standby mode. *1: watch prescaler counts but does not generate watch interrupts. *2: if the subclock is selected as the operating clock, in watch mode, lcd controller/driver operation must be enabled. *3: can be operated if watch prescaler output is selected as its operating clock.
101 3.7 standby modes (low-power consumption) 3.7.2 sleep mode this section describes the operations of sleep mode. n operation of sleep mode m changing to sleep mode sleep mode stops the cpu operating clock. the cpu stops while maintaining all register contents, ram contents, and pin states at their values immediately prior to entering sleep mode. however, peripheral functions except the watchdog timer continue to operate. if the system is in subclock mode, however, the main clock oscillation is stopped; and because the timebase timer operates on a divide-by-two version of the main clock source oscillation, it also stops operating. writing "1" to the sleep bit in the standby control register (stbc: slp) changes the cpu to sleep mode. if an interrupt request is generated when "1" is written to the slp bit, the write to the bit is ignored, and the cpu continues the instruction execution without change to sleep mode. (the cpu does not change to sleep mode even after completion of the interrupt processing.) m wake-up from sleep mode a reset or an interrupt from a peripheral function wakes up the cpu from sleep mode. if a reset occurs during sub-sleep mode on a product with power-on reset, the reset operation starts after the main clock oscillation stabilization delay time. in products without power-on reset, or if the reset occurs in main-sleep mode, there is no oscillation stabilization delay period. the reset operation also initializes the pin states. if an interrupt request with an interrupt level higher than "11" occurs from a peripheral function or an external interrupt circuit during sleep mode, the cpu wakes up from sleep mode, regardless of the interrupt enable flag (ccr: i) and interrupt level bits (ccr: il1 and il0) in the cpu. the normal interrupt operation is performed after wake-up from sleep mode. if the interrupt request is accepted, the cpu executes interrupt processing. if the interrupt request is not accepted, the cpu continues execution from the subsequent instruction following the instruction executed immediately before changing to sleep mode.
102 chapter 3 cpu 3.7.3 stop mode this section describes the operations of stop mode. n operation of stop mode m changing to stop mode stop mode the source oscillation. almost functions stop while maintaining all register and ram contents at their value immediately before changing to stop mode. if the system is in main clock mode, the main clock oscillation stops, but the subclock oscillation continues to run. this means that the watch prescaler can still count and some functions that run on the subclock can still function. except the external interrupt circuit, however, the cpu and other peripheral functions stop operating. if the system is in subclock mode, both the main and subclock oscillations are stopped. all chip functions other than external interrupt circuits stop. accordingly, data can be held with minimum power consumption. writing "1" to the stop bit in the standby control register (stbc: stp) changes the cpu to stop mode. at this time, external pin states are held if the pin state specification bit (stbc: spl) is "0" if spl is "1" external pins go to the high-impedance state. (pins with the pull-up resistor (optional) go to the "h" level.) if an interrupt request is generated when "1" is written to the stp bit, the write to the bit is ignored, and the cpu continues the instruction execution without change to stop mode. (the cpu does not assume stop mode even after completion of the interrupt processing.) prohibit interrupt request out from the timebase timer (tbtc: tbie = "0") before changing to stop mode in main clock mode as necessary. similarly, prohibita timeclock interrupt request output from the watch prescaler (wpcr: wie = "0") before changing to stop mode in subclock mode. m wake-up from stop mode a reset or an external interrupt wakes up the cpu from stop mode. if reset occurs during stop mode on a product with power-on reset, the reset operation starts after the main clock oscillation stabilization delay time. products without power-on reset do not require for the oscillation stabilization delay time after a reset in stop mode. the reset initializes pin states. if an interrupt request with an interrupt level higher than "11" occurs from an external interrupt circuit during stop mode, the cpu wakes up from stop mode, regardless of the interrupt enable flag (ccr: i) and interrupt level bits (ccr: il1, il0) in the cpu. only external interrupt requests can occur during stop mode because peripheral functions are stopped. in main-stop mode, the watch prescaler operates, but it does not generate watch interrupts. after wake-up from stop mode, the normal interrupt operation is performed after the oscillation stabilization delay time has passed. if the interrupt request is accepted, the cpu executes interrupt processing. if the interrupt request is not accepted, the cpu continues execution from the subsequent instruction following the instruction executed immediately before entering stop mode.
103 3.7 standby modes (low-power consumption) some peripheral functions restart from mid-operation when the cpu wakes up from stop mode by an external interrupt. the first interval time from the interval timer function, for example, is indeterminate. therefore, initialize all peripheral functions after wake-up from stop mode. check: only interrupt requests from external interrupt circuits can be used to wake up from stop mode by an interrupt.
104 chapter 3 cpu 3.7.4 watch mode this section describes the operations of watch mode. n operation of watch mode m changing to watch mode watch mode stops the clocks that clock the cpu and the main peripheral functions. you can go to watch mode only from subclock mode (in which the main clock oscillation is stopped). prior to going to watch mode, registers are saved and the contents of ram are held. all chip functions other than watch prescaler (timeclock interrupt), external interrupt circuit, and certain functions that run off of the subclock stop. accordingly, data can be held with extremely small power consumption. writing "1" to the timeclock bit in the standby control register (stbc: tmd) changes the cpu to watch mode. this can be done, however, only when the system clock select bit of the system clock control register (sycc: scs) is "0" (subclock mode active). when you go to watch mode, external pin states are held if the pin state specification bit in the standby control register (stbc: spl) is "0" if spl is "1" external pins go the high-impedance state. (pins with a pull-up resistor (optional) go to the "h" level) if an interrupt request is generated when "1" is written to the tmd bit, the write to the bit is ignored, and the cpu continues the instruction execution without change to watch mode. (the cpu does not assume watch mode even after completion of the interrupt processing.) m wake-up from watch mode a reset, a timeclock interrupt or an external interrupt wakes up cpu from watch mode. if a reset occurs during watch mode on a product with power-on reset, the reset operation starts after the main clock oscillation stabilization delay time. products without power-on reset do not require for the oscillation stabilization delay time after a reset in watch mode. the reset initializes pin states. if an interrupt request with an interrupt level higher than "11" occurs from a watch prescaler or an external interrupt circuit during watch mode, the cpu wakes up from watch mode, regardless of the interrupt enable flag (ccr:i) and interrupt level bits ((ccr: il1, il0) in the cpu. only timeclock or external interrupt requests can occur during watch mode because most of the peripheral functions except watch prescaler are stopped. after wake-up from stop mode, the normal interrupt operation is performed. if the interrupt request is accepted, the cpu executes interrupt processing. if the interrupt request is not accepted, the cpu continues execution from the subsequent instruction following the instruction executed immediately before entering watch mode. some peripheral functions restart from mid-operation when the cpu wakes up from watch mode. the first interval time from the interval timer function, for example, is indeterminate. therefore,initialize all peripheral functions after wake-up from watch mode.
105 3.7 standby modes (low-power consumption) 3.7.5 standby control register (stbc) the standby control register (stbc) controls the changing to sleep mode, stop mode, or watch mode, sets the pin states in stop mode and watch mode, and initiates software resets. n standby control register (stbc) figure 3.7-1 standby control register (stbc) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0008 h stp slp spl rst tmd 00010--- b wwr/www tmd watch bit valid only in subclock mode (sycc: scs = 0) read write 0 reading always returns "0". no effect on operation 1 changing to watch mode rst software reset bit read write 0 generates a reset signal for four instruction cycles. 1 reading always returns "1". no effect on operation spl pin state specification bit 0 external pins hold their states prior to entering stop mode or watch mode. 1 external pins go to high-impedance state on entering stop mode or watch mode. slp sleep bit read write 0 reading always returns "0". no effect on operation 1 change to sleep mode. stp stop bit read write 0 reading always returns "0". no effect on operation 1 change to stop mode. r/w : readable and writable w : write-only : unused x : indeterminate : initial value
106 chapter 3 cpu table 3.7-2 standby control register (stbc) bits bit function bit 7 stp: stop bit ? sets the cpu changing to stop mode. ? writing "1" to this bit sets the cpu changing to stop mode. ? writing "0" to this bit has no effect on operation. ? reading this bit always returns "0". bit 6 slp: sleep bit ? sets the cpu changing to sleep mode. ? writing "1" to this bit sets the cpu changing to sleep mode. ? writing "0" to this bit has no effect on operation. ? reading this bit always returns "0". bit 5 spl: pin state specification bit ? specifies the states of the external pins during stop mode and watch mode. ? writing "0" to this bit specifies that external pin hold their states (levels) on changing to stop mode or watch mode. ? writing "1" to this bit specifies that external pins to go to high impedance state on entering stop mode or watch mode. (pin with a pull-up resistor (optional) go to "h" level.) ? initialized to "0" by a reset. bit 4 rst: software reset bit ? specifies a software reset. ? writing "0" to this bit generates an internal reset source for four instruction cycles. ? writing "1" to this bit has no effect on operation. ? reading this bit always returns "1". note: when the software reset is applied in subclock mode, operation will start up in main clock mode after an oscillation stabilization delay time. for this reason, if the reset output option is selected, the rst signal will be output during the oscillation stabilization delay time. bit 3 tmd: watch bit ? sets the cpu changing to watch mode. ? a write to this bit is valid only in subclock mode (sycc: scs = 0). ? writing "1" to this bit sets the cpu changing to watch mode. ? writing "0" to this bit has no effect on operation. ? reading this bit always returns "0". bit 2 bit 1 bit 0 unused bits ? the read value is indeterminate. ? writing to these bits has no effect on operation.
107 3.7 standby modes (low-power consumption) 3.7.6 state transition diagram 1 (options: power-on reset, two clocks) this section shows the state transition diagram for products with power-on reset and dualclock options. n state transition diagram 1 (options: power-on reset, two clocks) figure 3.7-2 state transition diagram 1 (options: power-on reset, two clocks) power on oscillation stabilization delay reset state sub-run state reset state power-on reset main-stop mode main-run state main-sleep mode main clock mode main clock oscillation stabilization delay subclock oscillation stabilization delay subclock mode sub-run main clock oscillation stabilization delay sub-stop mode sub-sleep mode watch state <11> <3> <8> [8] <7> [7] [1] [2] [3] [3] [2] [1] [8] [5] [6] [4] [6] [5] <1> <2> <4> <5> <6> <9> <10> [7] [4]
108 chapter 3 cpu m changing to/wake-up from clock modes (non-standby modes) table 3.7-3 changing to/wake-up from clock modes (options: power-on reset, two clocks) state transition conditions/events required to transition changing to main-run state (normal main clock mode) after power-on reset [1] [2] main clock oscillation stabilization delay time complete. (timebase timer output) wake up from reset input. reset in main-run state [3] have external, software, or watchdog reset. changing from main-run state to sub-run state [4] sycc: scs=0* changing from sub-run state back to main-run state [5] [6] [7] sycc: scs=1 main clock oscillation stabilization delay time complete. (can be checked by looking at sycc: scm) have external, software, or watchdog reset. reset in sub-run state [8] have external, software, or watchdog reset. sycc: system clock control register *: changing to sub-run state at power-on occurs after the subclock oscillation stabilization delay time complete.
109 3.7 standby modes (low-power consumption) m changing to/wake-up from standby modes stbc: standby control register *: changing to watch mode is possible only from sub-run state (sycc: scs = 0). note: neither software nor watchdog resets can occur during standby because the cpu and watchdog timer are both stopped. table 3.7-4 changing to/wake-up from standby modes (options: power-on reset, two clocks) state transition conditions/events required to transition main clock mode subclock mode changing to sleep mode [1] stbc: slp = 1 <1> stbc: slp = 1 wake-up from sleep mode [2] [3] interrupt (any) external reset <2> <3> interrupt (any) external reset changing to stop mode [4] stbc: stp = 1 <4> stbc: stp = 1 wake-up from stop mode [5] [6] [7] [8] external interrupt main clock oscillation stabilization delay time complete. (have timebase timer output.) external reset external reset (during oscillation stabilization delay time) <5> <6> <7> <8> external interrupt subclock oscillation stabilization delay time ends.(have watch prescaler output.) external reset external reset (during oscillation stabilization delay time) changing to watch mode -<9> stbc: tmd = 1* wake-up from watch mode -<10> <11> external or watch interrupt external reset
110 chapter 3 cpu 3.7.7 state transition diagram 2 (options: no power-on reset, two clocks) this section shows the state transition diagram for products without power-on reset and dualclock options. n state transition diagram 2 (options: without power-on reset, two clocks) figure 3.7-3 state transition diagram 2 (options: without power-on reset, two clocks) po wer on oscillation stabilization delay reset state sub-run state reset state main-stop mode main-run state main-sleep mode main clock mode main clock oscillation stabilization delay subclock oscillation stabilization delay subclock mode sub-run main clock oscillation stabilization delay sub-stop mode sub-sleep mode watch state <11> <3> <8> [10] <7> [8] [1] external reset [2] [3] [3] [2] [1] [8] [5] [6] [4] [6] [5] <1> <2> <4> <5> <6> <9> <1 0> [7] [4] [7] [9]
111 3.7 standby modes (low-power consumption) m changing to/wake-up from clock modes (non-standby modes) table 3.7-5 changing to/wake-up from clock modes (options: without power-on reset, two clocks) state transition conditions/events required to transition changing to main-run state (normal main clock mode) after external reset [1] [2] external reset input must be held asserted until main clock oscillation has had time to stabilize. wake-up from reset input. reset in main-run state [3] have external, software, or watchdog reset. changing from main-run state to sub-run state [4] sycc: scs=0* changing from sub-run state back to main-run state [5] [6] [7] [8] sycc: scs=1 main clock oscillation stabilization delay time complete. (can be checked by looking at sycc: scm) have software or watchdog reset. have external reset. reset in sub-run state [9] [10] have software or watchdog reset have external reset sycc: system clock control register *: changing to sub-run state at power-on occurs after the subclock oscillation stabilization delay time complete.
112 chapter 3 cpu m changing to/wake-up from standby modes stbc: standby control register *: changing to watch mode is possible only from sub-run state (sycc: scs = 0). check: in all states except the main clock mode normal run (main-run) and sleep states, the external reset input must be held asserted until main clock oscillation has had time to stabilize. table 3.7-6 changing to/wake-up from standby modes (options: without power-on reset, two clocks) state transition conditions/events required to transition main clock mode subclock mode changing to sleep mode [1] stbc: slp = 1 <1> stbc: slp = 1 wake-up from sleep mode [2] [3] interrupt (any) external reset <2> <3> interrupt (any) external reset changing to stop mode [4] stbc: stp = 1 <4> stbc: stp = 1 wake-up from stop mode [5] [6] [7] [8] external interrupt main clock oscillation stabilization delay time complete. (have timebase timer output.) external reset external reset (during oscillation stabilization delay time) <5> <6> <7> <8> external interrupt subclock oscillation stabilization delay time complete. (watch prescaler output.) external reset external reset (during oscillation stabilization delay time) changing to watch mode -<9> stbc: tmd = 1* wake-up from watch mode -<10> <11> external or watch interrupt external reset
113 3.7 standby modes (low-power consumption) 3.7.8 state transition diagram 3 (one-clock option) this section shows two state transition diagrams for one-clock option products: one diagram for "with power-on reset" option products and one for "without power-on reset" products. there are no subclock or watch modes when one clock is used. n state transition diagram 3 (one-clock option) figure 3.7-4 state transition diagram 3 (products with power-on reset) figure 3.7-5 state transition diagram 3 (products without power-on reset) power on oscillation stabilization delay reset state reset state power-on reset main-stop mode main-run state main-sleep mode main clock mode main clock oscillation stabilization delay [1] [2] [3] [3] [2] [1] [8] [5] [6] [7] [4] power-on reset state main-stop mode main-run state main-sleep mode main clock mode main clock oscillation stabilization delay [1] external reset [2] [3] [3] [2] [1] [5] [6] [7] [4] [8]
114 chapter 3 cpu m changing to normal state (run) and reset m changing to/wake-up from standby mode stbc: standby control register table 3.7-7 changing to main clock mode run state and reset (one-clock option) state transition conditions/events required to transition products with power-on reset (figure 3.7-4 "state transition diagram 3 (products with power-on reset)") products without power-on reset (figure 3.7-5 "state transition diagram 3 (products without power- on reset)") changing to normal state (run) after power-on [1] [2] main clock oscillation stabilization delay time complete. (timebase timer ouptput.) wake-up from reset input. [1] [2] external reset input must be held asserted until main clock oscillation has had time to stabilize. reset in run state [3] have external, software, or watchdog reset. [3] have external, software, or watchdog reset. table 3.7-8 changing to/wake-up from standby modes (options: power-on reset, two clocks) state transition conditions/events required to transition products with power-on reset (figure 3.7-4 "state transition diagram 3 (products with power-on reset)") products without power-on reset (figure 3.7-5 "state transition diagram 3 (products without power- on reset)") changing to sleep mode [1] stbc: slp = 1 [1] stbc: slp = 1 wake-up from sleep mode [2] [3] interrupt external reset [2] [3] interrupt external reset changing to stop mode [4] stbc: stp = 1 [4] stbc: stp = 1 wake-up from stop mode [5] [6] [7] [8] external interrupt main clock oscillation stabilization delay time complete. (timebase timer output.) external reset external reset (during oscillation stabilization delay time) [5] [6] [7] [8] external interrupt main clock oscillation stabilization delay time complete. (timebase timer output.) external reset external reset (during oscillation stabilization delay time)
115 3.7 standby modes (low-power consumption) 3.7.9 notes on using standby modes the cpu does not change to a standby mode if an interrupt request occurs from a peripheral function when a standby mode is set in the standby control register. (stbc) also, if an interrupt is used to wake up from a standby mode to the normal operating state, the operation after wake-up differs depending on whether or not the interrupt request is accepted. n changing to a standby mode and interrupts if an interrupt request with an interrupt level higher than "11" occurs from a peripheral function to the cpu, writing "1" to the stop bit (stp), sleep bit (slp), or watch bit (tmd) in the standby control register (stbc) is ignored. therefore, the cpu does not change to a standby mode. (the cpu also does not change to the standby mode after completing interrupt processing.) this does not depend on whether or not the cpu accepts the interrupt. even if the cpu is currently performing interrupt processing, the interrupt request flag bit is cleared and, if no other interrupt request is present, the device can change to the standby mode. n wake-up from standby mode by interrupt if an interrupt request with an interrupt level higher than "11" occurs from a peripheral function or others during sleep or stop mode, the cpu wakes up from a standby mode. this does not depend on whether or not the cpu accepts the interrupt. after wake-up from a standby mode, the cpu performs the normal interrupt operations. if the level set in the interrupt level setting register (ilr1 to ilr3) corresponding to the interrupt request is higher than the interrupt level bits in the condition code register (ccr: il1, il0), and if the interrupt enable flag is enabled (ccr: i = "1"), the cpu branches to the interrupt processing routine. if the interrupt is not accepted, operation restarts from the instruction following the instruction that activated a standby mode. to prevent control from branching to an interrupt processing routine after wake-up, take measures such as disabling interrupts before setting a standby mode. n notes on setting standby mode when setting the standby control register (stbc) to go to a standby mode, make the settings in accordance with table 3.7-9 "standby control register (stbc) low-power consumption mode settings". the order of precedence as to which mode will be activated if more than one bit is set to "1" is "stop" mode, "watch" mode, and "sleep" mode. other factors being equal, it is best to set "1" for just one bit. also avoid going to stop, sleep, or watch mode immediately after switching from subclock to main clock mode (sycc: scs=0 --> 1). first verify that the clock monitor bit (sycc: scm) of the system control register is "1", then make the standby mode change.
116 chapter 3 cpu note that you cannot go to the watch standby mode when operating in main clock mode. (a write to the tmd bit will be ignored.) n oscillation stabilization delay time as the oscillator that provides the source oscillation is stopped during stop mode in both main clock mode and subclock mode, a delay time is required for oscillation to stabilize after the oscillator restarts operation. in main clock mode, the main clock oscillation stabilization delay time is selected from one of four possible delay times defined by the timebase timer. in subclock mode, the subclock oscillation stabilization delay time is defined by the watch prescaler. in main clock mode, if the interval time set for the timebase timer is less than the oscillation stabilization delay time, the timebase timer generates an interval timer interrupt request before the end of the oscillation stabilization delay time. to prevent this, disable the interrupt request output for the timebase timer (tbtc: tbie = "0") before changing to stop mode in main clock mode as necessary. selection of a watch prescaler interrupt interval shorter than the oscillation stabilization delay time will similarly cause the watch interrupt request to be generated during the oscillation stabilization delay time.to prevent this, disable the watch interrupt request output for the watch prescaler (wpcr: wie =0) before changing to stop mode in subclock mode as necessary. table 3.7-9 standby control register (stbc) low-power consumption mode settings stbc register mode stp (bit 7) slp (bit 6) tmd (bit 3) 000normal 001watch 010sleep 100stop
117 3.8 memory access mode 3.8 memory access mode in the mb89980 series, the only memory access mode is the single-chip mode. n single-chip mode in single-chip mode, the device uses internal ram and rom only. therefore, the cpu can access no areas other than the internal i/o area, ram area, and rom area (internal access). n mode pins (mod1, mod0) always set the mode pins, mod1 and mod0, for v ss at reset, reads the mode data and reset vector from internal rom. do not change the mode pin settings, even after completion of the reset (i.e. during normal operation). table 3.8-1 "mode pin setting" lists the mode pin settings. n mode data always set the mode data in internal rom to "00 h " to select single-chip mode. figure 3.8-1 mode data structure table 3.8-1 mode pin setting pin state description mod1 mod0 v ss v ss reads the mode data and reset vector from internal rom v ss v cc prohibited settings v cc v ss v cc v cc bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 address fffd h data operation 00 h selects single-chip mode. other than 00 h reserved. do not set this value.
118 chapter 3 cpu n memory access mode selection operation only the single-chip mode can be selected. table 3.8-2 mode pins and mode data lists the mode pin and mode data options. figure 3.8-2 "memory access selection operation" shows the operation for memory access mode selection. figure 3.8-2 memory access selection operation table 3.8-2 mode pins and mode data memory access mode mode pins (mod1, mod0) mode data single-chip mode v ss , v ss 00 h other modes prohibited settings prohibited settings check mode pins delay for wake-up from (external reset or reset source oscillation stabilization delay time) mode fetch check mode data set i/o pin functions for program execution (run) reset source generated mode pins (mod1, mod0) read mode data from internal rom i/o pins are high impedance reset active? fetch mode data and reset vector from internal rom. mode data single-chip mode (00 h ) set i/o pins to input or output depending on their respective port data direction registers (ddr), etc. i/o pins are available as ports single-chip mode v ss , v ss prohibited setting other prohibited setting other
119 chapter 4 i/o ports this chapter describes the functions and operation of the i/o ports. 4.1 "overview of i/o ports" 4.2 "port 0 and port 1" 4.3 "port 2" 4.4 "port 3" 4.5 "ports 4, 6 and 7" 4.6 "port 5" 4.7 "program example for i/o ports"
120 chapter 4 i/o ports 4.1 overview of i/o ports the i/o ports consist of eight ports (47 pins) including input-only, output-only and general-purpose i/o ports (parallel i/o ports). the ports also serve as peripherals (i/o pins of peripheral functions). n i/o port functions the functions of the i/o ports are to output data from the cpu via the i/o pins and to fetch signals input to the i/o pins into the cpu. input and output are performed via the port data registers (pdr). also, for certain ports the direction of each i/o pin can be individually set to either input or output for each bit by the port data direction register (ddr). the following lists the functions of each port and the peripheral with which the ports also serve as. table 4.1-1 "port function" lists the functions of each port and table 4.1-2 "port registers" lists the registers for each port. ? port 0: general-purpose i/o port. also serves as peripherals (external interrupt 2 pins). ? port 1: general-purpose i/o port. also serves as peripherals (external interrupt 1 pins). ? port 2: general-purpose i/o port. also serves as peripherals (timer, pwm 2, remote control pins). ? port 3: port 3: output-only port (p30) and input-only port (p31 and p32). also serves as peripherals (pwm 1, buzzer output and sub-clock pins). ? port 4: output-only port. also serves as peripherals (lcdc segment output pins). ? port 5: output-only port. also serves as peripherals (analog input pins). ? port 6: port 6: output-only port. also serves as peripherals (lcdc segment output pins). ? port 7: output-only port. also serves as peripherals (lcdc common output pins).
121 4.1 overview of i/o ports *1: ports 4, 6, and 7 are output ports only when the ports are selected. *2 p30 is cmos output and p31 and p32 are cmos input only. *3: pinsp40 to p47, p21, p26, p27, p60 and p61have high current drive-type output circuits. table 4.1-1 port function port pin name input type output type function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port0 p00/int20 to p07/int27 cmos (resource: hysteresis) cmos general-purpose i/o port p07 p06 p05 p04 p03 p02 p01 p00 external interrupts 2 int27 int26 int25 int24 int23 int22 int21 int20 port1 p10/int10 to p13/int13 p14 to p17 general-purpose i/o port p17 p16 p15 p14 p13 p12 p11 p10 external interrupts 1 int13 int12 int11 int10 port2 p20/ec to p27/pwm2 n-ch open-drain* 3 general-purpose i/o port p27 p26 p25 p24 p23 p22 p21 p20 peripherals pwm2 rco to ec port3 p30/pwm1/ bz to p32/ x1a *2 cmos general-purpose i/o *2 p32 p31 p30 periphera ls x1 ax0a pwm1/ bz port4 p40/seg0 to p47/seg7 n-ch open-drai n *1, * 3 output-only port p47 p46 p45 p44 p43 p42 p41 p40 lcdc segment output seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 port5 p50/an0 to p53/an3 analog channel selector n-ch open- drain output-only port p53 p52 p51 p50 analog input an3 an2 an1 an0 port6 p60/seg8 to p65/seg13 n-ch open-drain *1 output-only port p65 p64 p63 p62 p61 p60 lcdc segment output seg13 seg12 seg11 seg10 seg9 seg8 port7 p70/com2, p71 /com3 output-only port p71 p70 lcdc common output com3 com2
122 chapter 4 i/o ports * bit manipulation instructions cannot be used on ddr0, ddr1, and ddr2. r/w: readable and writable r: read-only w: write-only x: indeterminate table 4.1-2 port registers register read/write address initial value port 0 data register (pdr0) r/w 0000 h xxxxxxxx b port 0 data direction register (ddr0) w* 0001 h 00000000 b port 0 pull-up control register (purr0) r/w 0040 h 11111111 b port 1 data register (pdr1) r/w 0002 h xxxxxxxx b port 1 data direction register (ddr1) w* 0003 h 00000000 b port 1 pull-up control register (purr1) r/w 0041 h 11111111 b port 2 data register (pdr2) r/w 0004 h xxxxxxxx b port 2 data direction register (ddr2) w* 0005 h 00000000 b port 3 data register (pdr3) r/w 000c h xxxxxxx1 b port 4 data register (pdr4) r/w 000e h 11111111 b port 5 data register (pdr5) r/w 000f h xxxx1111 b port 5 pull-up control register (purr5) r/w 0042 h xxxx1111 b port 6 data register (pdr6) r/w 0012 h xx111111 b port 7 data register (pdr7) r/w 0013 h xxxxxx11 b
123 4.2 port 0 and port 1 4.2 port 0 and port 1 port 0 and port 1 are general-purpose i/o ports that also serve as input pins for external interrupts. this section principally describes the port functions when operating as general- purpose i/o ports. the section describes the port structure and pins, the pin block diagram, and the registers for port 0 and port 1. n structure of port 0 and port 1 port 0 and port 1 consist of four components respectively. m port 0 ? general-purpose i/o pins/external interrupt 2 input pins (p00/int20 to p07/int27 ) ? port 0 data register (pdr0) ? port 0 data direction register (ddr0) ? port 0 pull-up control register (purr0) (only available in mb89p985 and mb89pv980) m port 1 ? general-purpose i/o pins/external interrupt 1 input pins (p10/int10 to p13/int13) and general-purpose i/o pins (p14 to p17) ? port 1 data register (pdr1) ? port 1 data direction register (ddr1) ? port 1 pull-up control register (purr1) (only available in mb89p985 and mb89pv980) n port-0 and port-1 pins port 0 and port 1 both consist of eight i/o pins of a cmos input and cmos output type respectively. when p00/int20 to p07/int27 (port 0) and p10/int10 to p13/int13 (port 1) are used as input pins, they can also be used as external interrupt input pins.
124 chapter 4 i/o ports * external interrupt inputs are hysteresis inputs. reference: see section 1.7 "i/o pins and pin functions" for a description of the circuit type. table 4.2-1 port-0 and port-1 pins port pin name function shared peripheral i/o type circuit type input output mb89983 mb89p985 mb89pv980 port 0 p00/int20 to p07/int27 general- purpose i/o external interrupt 2 cmos* cmos e f port 1 p10/int10 to p13/int13 external interrupt 1 p14 to p17 - cmos g h
125 4.2 port 0 and port 1 n block diagram of port-0 and port-1 pin figure 4.2-1 block diagram of port-0 and port-1 pin for mb89983 figure 4.2-2 block diagram of port-0 and port-1 pin for mb89p985 and mb89pv980 check: when a port is used as a normal input port, external interrupt circuit operation that use the same pins must be disabled. see chapter 9 "external interrupt circuit 1" and chapter 10 "external interrupt circuit 2" for details. pdr (port data register) ddr internal data bus pdr read pdr read (for bit manipulation instructions) output latch pdr write ddr write (port data direction register) pin spl: pin state specification bit in the standby control register (stbc) n-ch p-ch stop, watch mode (spl = 1) to external interrupt circuit external interrupt input enable p00 to p07 and p10 to p13 only stop, watch mode (spl=1) pull-up resistor (approx. 50 k /5.0 v) r p-ch pdr (port data register) ddr internal data bus pdr read pdr read (for bit manipulation instructions) output latch pdr write ddr write (port data direction register) pin spl: pin state specification bit in the standby control register (stbc) n-ch p-ch p-ch stop, watch mode (spl = 1) to external interrupt circuit external interrupt input enable p00 to p07 and p10 to p13 only stop, watch mode (spl=1) pull up control register pull-up resistor (approx. 50 k /5.0 v)
126 chapter 4 i/o ports check: mb89983 can be set with a pull-up resistor by mask option check: mb89p985 and mb89pv980 can be set with a pull-up resistor by software (pull-up control register) n port-0 and port-1 registers the port-0 registers consist of pdr0, ddr0 and purr0. the port-1 registers consist of pdr1, ddr1 and purr1. each bit in these registers has a one-to-one relationship with port-0 and port-1 pin respectively. table 4.2-2 "correspondence between pin and register for port-0 and port-1" shows the correspondence between pins and registers for port-0 and port-1. table 4.2-2 correspondence between pin and register for port-0 and port-1 port correspondence between register bit and pin port 0 pdr0,ddr0,purr0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 corresponding pin p07 p06 p05 p04 p03 p02 p01 p00 port 1 pdr1,ddr1,purr1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 corresponding pin p17 p16 p15 p14 p13 p12 p11 p10
127 4.2 port 0 and port 1 4.2.1 port-0 and port-1 registers (pdr0, pdr1, purr0 ddr0, ddr1, purr1) this section describes the port-0 and port-1 registers. n port-0 and port-1 register functions m port 0, 1 data registers (pdr0, pdr1) the pdr0 and pdr1 registers hold the pin states. therefore, a bit corresponding to a pin set as an output port can be read as the same state ("0" or "1" as the output latch, but when it is an input port, it cannot be read as the output latch state. note: for setb and clrb bit operation instructions, since the state of output latch (not the pin) is read, the output latch states of bits other than those being operated on are not changed. m port 0, 1 data direction registers (ddr0, ddr1) the ddr0 and ddr1 registers set the direction (input or output) for each pin (bit). setting "1" to the bit corresponding to a port (pin) sets the pin as an output port. setting "0" sets the pin as an input port. check: as the ddr0 and ddr1 registers are write-only, the bit manipulation instructions (setb and clrb) cannot be used. m settings when pins are used as external interrupt inputs when port pins are used as external interrupt input pins, in addition to enabling the interrupt circuit (external interrupt 1 or 2), the corresponding pins must also be set as inputs. (the corresponding output latch data has no significance in this case.) table 4.2-3 "port-0 and port-1 register function" lists the functions of the port-0 and port-1 registers. table 4.2-3 port-0 and port-1 register function register data read write read/ write address initial value port 0 data register (pdr0) 0pin state is the "l" level. sets "0" to the output latch. outputs an "l" level to the pin if the pin functions as an output port. r/w 0000 h xxxxxxxx b 1pin state is the "h" level. sets "1" to the output latch. outputs an "h" level to the pin if the pin functions as an output port.
128 chapter 4 i/o ports r/w: readable and writable w: write-only x: indeterminate m port 0, 1 pull-up control registers (purr0, purr1) by using pull-up resistor option in each pin for port 0, 1, setting is possible bit by bit when writing to pull-up control register for mb89p985 and mb89pv980 only. the pull-up resistor for mb89983 is selected by mask option. when pull-up resistor is selected in pull-up register in stop and clock mode (spl=1). the state of these pin are in "h" level (pull up state) rather than high impedance. however, during reset, pull up is unavailable and will be in high impedance state. figure 4.2-3 "pull up control registers setting (purr0)" and figure 4.2-4 "pull up control registers setting (purr0, purr1)" are list of the pull-up resistor option setting of purr0 and purr1 port 0 data direction register (ddr0) 0 reading is not permitted (write-only). disables output transistor and sets the pin as an input pin. w0001 h 00000000 b 1 enables output transistor and sets the pin as output pin. port 1 data register (pdr1) 0pin state is the "l" level. sets "0" to the output latch. outputs an "l" level to the pin if the pin functions as an output port. r/w 0002 h xxxxxxxx b 1pin state is the "h" level. sets "1" to the output latch. outputs an "h" level to the pin if the pin functions as an output port. port 1 data direction register (ddr1) 0 reading is not permitted. (write-only.) disables output transistor and sets the pin as an input pin. w0003 h 00000000 b 1 enables output transistor and sets the pin as output pin. table 4.2-3 port-0 and port-1 register function register data read write read/ write address initial value
129 4.2 port 0 and port 1 figure 4.2-3 pull up control registers setting (purr0) figure 4.2-4 pull up control registers setting (purr0, purr1) note: for mb89p985 and mb89pv980, there will be current leakage through the pull-up resistor in stop mode when the pull-up resistor is enabled and these ports are input "0". to prevent the current leakage, the pull-up resistor should be disabled before going into stop mode. purr0 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0040 h pur07 pur06 pur05 pur04 pur03 pur02 pur01 pur00 11111111 h rw r/w rw r/w rw r/w rw r/w pur03 pur02 pur01 pur00 0 p03 pull up on p02 pull up on p01 pull up on p00 pull up on 1 p03 pull up off p02 pull up off p01 pull up off p00 pull up off pur07 pur06 pur05 pur04 0 p07 pull up on p06 pull up on p05 pull up on p04 pull up on 1 p07 pull up off p06 pull up off p05 pull up off p04 pull up off purr1 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0041 h pur17 pur16 pur15 pur14 pur13 pur12 pur11 pur10 11111111 h rw r/w rw r/w rw r/w rw r/w pur13 pur12 pur11 pur10 0 p13 pull up on p12 pull up on p11 pull up on p10 pull up on 1 p13 pull up off p12 pull up off p11 pull up off p10 pull up off pur17 pur16 pur15 pur14 0 p17 pull up on p16 pull up on p15 pull up on p14 pull up on 1 p17 pull up off p16 pull up off p15 pull up off p14 pull up off
130 chapter 4 i/o ports 4.2.2 operation of port 0 and port 1 this section describes the operations of the port 0 and port 1. n operation of port 0 and port 1 m operation as an output port ? setting the corresponding ddr0 or ddr1 register bit to "1" sets a pin as an output port. ? when a pin is set as an output port, its output transistor is enabled and the pin outputs the data stored in the output latch. ? writing data to the pdr0 and pdr1 registers stores the data in the output latch and outputs the data directly to the pin. ? reading the pdr0 or pdr1 register returns the pin value. m operation as an input port ? setting the corresponding ddr0 or ddr1 register bit to "0" sets a pin as an input port. ? when a pin is set as an input port, the output transistor is "off" and the pin goes to the high-impedance state. ? writing data to the pdr0 and pdr1 registers stores the data in the output latch but does not output the data to the pin. ? reading the pdr0 or pdr1 register returns the pin value. m operation as an external interrupt input ? when a port is an external interrupt input, the port is made an input by setting the corresponding ddr0 or ddr1 register bits to "0". ? reading the pdro or pdr1 register returns the pin value, regardless of whether external interrupt inputs or interrupt request outputs are enabled/disabled. m operation at reset ? resetting the cpu initializes the ddr0 and ddr1 register values to "0". this sets the output transistors "off" (all pins become input ports) and sets the pins to the high- impedance state. ? the pdr0 and pdr1 registers are not initialized by a reset. therefore, to use as output ports, the output data must be set in the pdr0 and pdr1 registers before setting the corresponding ddr0 or ddr1 register bits to output mode. m operation in stop and watch modes the pins go to the high-impedance state if the pin state specification bit in the standby control register (stbc: spl) is "1" when the device changes to stop or watch mode. this is achieved by forcibly setting the output transistor "off" regardless of the ddr0 and ddr1 register values. to avoid current leakage, it is recommended to remain a known logic level of the input port pins during the standby mode.
131 4.2 port 0 and port 1 table 4.2-4 "port-0 and port-1 pin state" lists the port-0 and port-1 pin states. spl: pin state specification bit in the standby control register (stbc) hi-z: high impedance note: pins with a pull-up resistor go to the "h" level (pull-up state) rather than to the high- impedance state when the output transistors are all "off". table 4.2-4 port-0 and port-1 pin state pin name normal operation main-sleep mode main-stop mode (spl=0) sub-sleep mode sub-stop mode (spl=0) watch mode (spl=0) main-stop mode (spl = 1) sub-stop mode (spl = 1) watch mode (spl = 1) reset p00/int20 to p07/ int27 general-purpose i/o ports/ external interrupt input hi-z (external interrupt input) hi-z p10/int10 to p13/ int13 p14 to p17
132 chapter 4 i/o ports 4.3 port 2 port 2 is a general-purpose i/o port that also serves as the resource signal i/o pins. individual pins can be switched in units of a bit between the port and resource functions. this section principally describes the port functions when operating as a general-purpose i/o port. the section describes the port structure and pins, the pin block diagram, and the port registers for port 2. n structure of port 2 port 2 consists of the following three components: ? general-purpose i/o port/resource i/o pins (p20/ec to p27/pwm2) ? port 2 data register (pdr2) ? port 2 data direction register (ddr2) n port-2 pins port 2 consists of eight i/o pins of a cmos input, an n-ch open-drain output types. three of these pins are also used as signal i/o pins for various resources. while they are being used by the resource, these pins cannot be used as the general-purpose i/o port. some pin outputs are high current drive-type outputs.
133 4.3 port 2 table 4.3-1 "port-2 pin" lists the port-2 pins. *1: peripheral inputs are hysteresis inputs. *2: p21, p26, and p27 have high current drive-type outputs. reference: see section 1.7 "i/o pins and pin functions" for a description of the circuit type. table 4.3-1 port-2 pin port pin name function shared peripheral i/o type circuit type input output mb89983 mb89p985 mb89pv980 port 2 p20/ec p20 general- purpose i/o ec 8/16-bit timer, pulse input cmos* 1 n-ch open- drain* 2 jk p21 p21 general- purpose i/o -cmos lm p22/to p22 general- purpose i/o to 8/16-bit timer, timer output p23 p23 general- purpose i/o -cmos p24/ rco p24 general- purpose i/o rco remote control output cmos p25 p25 general- purpose i/o -cmos p26 p26 general- purpose i/o -cmos p27/ pwm2 p27 general- purpose i/o pwm 2 8-bit pwm timer 2, timer output
134 chapter 4 i/o ports n block diagram of port-2 pin figure 4.3-1 block diagram of port-2 pin for mb89983 figure 4.3-2 block diagram of port-2 pin for mb89p985 and mb89pv980 note: peripheral inputs continuously are input the pin value (except during stop and watch modes). pdr (port data register) ddr internal data bus pdr read pdr read (for bit manipulation instructions) output latch pdr write ddr write pin spl: pin state specification bit in the standby control register (stbc) n-ch stop, watch mode (spl = 1) to peripheral input p20 only (port data direction register) peripheral output peripheral output enable p22, p24 and p27 only stop, watch mode pins p21, p26, and p27 are high current drive-type outputs. pull-up resistor (approx. 50 k /5.0 v) r pdr (port data register) ddr internal data bus pdr read pdr read (for bit manipulation instructions) output latch pdr write ddr write pin spl: pin state specification bit in the standby control register (stbc) n-ch stop, watch mode (spl = 1) to peripheral input p20 only (port data direction register) peripheral output peripheral output enable p22, p24 and p27 only stop, watch mode pins p21, p26, and p27 are high current drive-type outputs
135 4.3 port 2 check: mb89983 can be set with a pull-up resistor by mask option n port-2 registers the port-2 registers consist of pdr2 and ddr2. each bit in these registers has a one-to-one relationship with a port 2 bit and port 2 pin. table 4.3-2 "port-2 register function" shows the correspondence between pins and registers for port 2. table 4.3-2 correspondence between pin and register for port 2 port correspondence between register bit and pin port 2 pdr2, ddr2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 corresponding pin p27 p26 p25 p24 p23 p22 p21 p20
136 chapter 4 i/o ports 4.3.1 port-2 registers (pdr2, ddr2) this section describes the port-2 registers. n port-2 register functions m port 2 data register (pdr2) the pdr2 register holds the pin states. therefore, when used as an output port that is not a peripheral output, it reads out as the same state ("0" or "1") as that of the output data latch; and when it is an input port, the output latch state cannot be read out. note: as the bit manipulation instructions (setb and clrb) read the output latch data rather than the pin level, the instructions do not change the output latch values for bits other than the bit being set or cleared. m port 2 data direction register (ddr2) the ddr2 register sets the direction (input or output) for each pin (bit). setting "1" to the bit corresponding to a port (pin) sets the pin as an output port. setting "0" sets the pin as an input port. check: as the ddr2 register is write-only, the bit manipulation instructions (setb and clrb) cannot be used. m settings as a peripheral output to use a peripheral that has an output pin, set the peripheral output enable bit for that pin to the "enable" state. as can be seen in the block diagram, the peripheral has precedence over the general-purpose port for use of the output pin. once the peripheral output is enabled, the states set in the pdr2 and ddr2 registers are no longer valid, and do not affect the data output by the peripheral, or the enabling of the output. m settings as a peripheral input to use a peripheral that has a port 2 pin as an input pin, set that pin as an input port. the output latch data for that pin will no longer be valid. table 4.3-3 "port-2 register function" lists the functions of the port-2 registers.
137 4.3 port 2 r/w: readable and writable w: write-only x: indeterminate *: pins with a pull-up resistor, go to the pull-up state. table 4.3-3 port-2 register function register data read write read/ write address initial value port 2 data register (pdr2) 0pin state is the "l" level. outputs an "l" level to the pin if the pin functions as an output port. (sets "0" to the output latch and turns the output transistor "on") r/w 0004 h xxxxxxxx b 1pin state is the "h" level. sets the pin to the high- impedance state if the pin functions as an output port*. (sets "1" to the output latch and turns the output transistor "off") port 2 data direction register (ddr2) 0 reading is not permitted (write-only). disables the output transistor and sets the pin as an input pin. w0005 h 00000000 b 1 enables the output transistor and sets the pin as an output pin.
138 chapter 4 i/o ports 4.3.2 operation of port 2 this section describes the operations of the port 2. n operation of port 2 m operation as an output port ? setting the corresponding ddr2 register bit to "1" sets a pin as an output port. ? when a pin is as an output port, the output transistor is enabled. when the output latch value is "0", the output transistor turns "on" and an "l" level is output from the pin. when the output latch value is "1" the transistor turns "off" and the pin goes to the high-impedance state. if a pull-up is set to the output pin, the pin goes to the pull-up state when the output latch value is "1". ? writing data to the pdr2 register stores the data in the output latch and outputs the data to the pin. ? reading the pdr2 register returns the pin value. m operation as an input port ? setting the corresponding ddr2 register bit to "0" sets a pin as an input port. ? when a pin is set as an input port, the output transistor is "off" and the pin goes to the high-impedance state. ? writing data to the pdp2 register stores the data in the output latch but does not output the data to the pin. ? reading the pdr2 register returns the pin value. m operation as a peripheral output ? if a peripheral output enable bit is set to "enable", the corresponding pin becomes a peripheral output. ? as the pin value can be read even if the peripheral output is enabled, the peripheral output value can be read via the pdr2 register. m operation as a peripheral input ? a port pin is set as a peripheral input by setting the corresponding ddr2 register bit to "0". ? reading the pdr2 register returns the pin value, regardless of whether or not the peripheral is using the input pin. m operation at reset ? resetting the cpu initializes the ddr2 register value to "0". this sets output transistors "off" (pins become input ports) and sets the pins to the high-impedance state. ? the pdr2 register is not initialized by a reset. therefore, to use as output ports, the output data must be set in the pdr2 register before setting the corresponding ddr2 register bit to output mode. ? pin state of p27 is undetermined until the internal clock starts operation.
139 4.3 port 2 m operation in stop and watch modes the pins go to the high-impedance state, if the pin state specification bit in the standby control register (stbc: spl) is "1" when the device changes to stop or watch mode. this is achieved by forcibly setting the output transistor "off" regardless of the ddr2 register value. table 4.3-4 "port-0 and port-1 pin state" lists the port-2 pin states. spl: pin state specification bit in the standby control register (stbc) hi-z: high impedance note: pins with a pull-up resistor go to the "h" level (pull-up state) rather than to the high- impedance state when the output transistor is turned "off". *: pin state of p27 is undetermined until the internal clock starts operation. table 4.3-4 port-0 and port-1 pin state pin name normal operation main-sleep mode main-stop mode (spl=0) sub-sleep mode sub-stop mode (spl=0) watch mode (spl=0) main-stop mode (spl = 1) sub-stop mode (spl = 1) watch mode (spl = 1) reset p20/ec to p27/ pwm2 general-purpose i/o port/ peripheral i/o hi-z hi-z
140 chapter 4 i/o ports 4.4 port 3 p30 is an output-only port and p31 and p32 are input-only ports that also serves as peripheral output. each pin can be switched between peripheral and port operation in bit units. the section describes the port structure and pins, the pin block diagram, and the port registers for port 3. n structure of port 3 port 3 consist of the following two components: ? cmos i/o pins/peripheral output pins (p30/pwm1/bz to p32/x1a) ? port 3 data register (pdr3) n port-3 pins port 3 has three output-only pins: two hysteresis inputs and one cmos output. table 4.4-1 "port-3 pin" lists the port-3 pins. reference: see section 1.7 "i/o pins and pin functions" for a description of the circuit type. table 4.4-1 port-3 pin port pin name function shared peripheral i/o type circuit type input output port 3 p30/pwm1/bz p30 cmos output pwm 1 output for the 8-bit pwm timer/ counter or buzzer output -cmosi p31/x0a p31 hysteresis input sub-clock x0a hystersis - r/b p32/x1a p32 hysteresis input sub-clock x1a hystersis - r/b
141 4.4 port 3 n block diagram of port-3 pin figure 4.4-1 block diagram of port-3 pin n port-3 registers the port-3 registers consist of pdr3. each bit in pdr3 registers has a one-to-one relationship with a port-3 pin. table 4.4-2 "correspondence between pin and register for port 3" shows the correspondence between pins and registers for port 3. pdr (port data register) internal data bus pdr read output latch pdr write pin spl: pin state specification bit in the standby control register (stbc) n-ch p-ch peripheral output peripheral output enable mask option sub-clock stop, watch mode (spl = 1) p31 and p32 only p30 only pdr table 4.4-2 correspondence between pin and register for port 3 port correspondence between register bit and pin port 3 pdr3, ddr3 - - - - - bit 2 bit 1 bit 0 corresponding pin - - - - - p32 p31 p30
142 chapter 4 i/o ports 4.4.1 port-3 register (pdr3) this section describes the port-3 register. n port-3 register functions m port 3 data register (pdr3) the pdr3 register holds the output latch states. therefore, it does not read out as the pin states or peripheral output data. m settings as a peripheral output when using peripherals that have output pins, set the peripherals output enable bit for that pin to the "enable" state. since the peripheral has precedence over the port for use of the output pin, once the peripheral output is enabled, the data in the pdr3 register has no significance, and has no affect on the data output by the peripheral, or the enabling of the output. table 4.4-3 "port-3 register function" lists the functions of the port-3 registers. r/w: readable and writable x: indeterminate table 4.4-3 port-3 register function register data read write read/ write address initial value port 3 data register (pdr3) 0 output latch value is "0". sets "0" to the output latch. outputs an "l" level to the pin. r/w 000c h xxxxxxx1 b 1 output latch value is "1". sets "1" to the output latch. outputs an "h" level to the pin.
143 4.4 port 3 4.4.2 operation of port 3 this section describes the operations of the port 3. n operation of port 3 m operation as an output port (p30/pwm1/bz only) ? writing data to the pdr3 register stores the data in the output latch. the pin outputs the data stored in the output latch at p30. ? reading the pdr3 register always returns the output latch value. m operation as a peripheral output (p30/pwm1/bz only) ? setting the output enable bit of the peripheral to "enable" makes the corresponding pin a peripheral output. ? you cannot read the peripheral output value by reading pdr3. (pdr3 contains the output latch value.) m operation as an input port (p31/x0a and p32/x1a only) ? writing data to the pdr3 registers stores the data in the output latch but does not output the data to the pin. ? reading the pdr3 register returns the pin value. ? for single clock product, if p31 and p32 are not used as input pins, p31 and p32 should be connected to pull-up or pull-down resistor. m operation at reset ? resetting the cpu initializes the pdr3 register values to "1". this outputs "h" level at p30. p31 and p32 are input pins. ? pin state of p30 is undetermined until the internal clock starts operation. m operation in stop and watch modes ? the output transistors are forcibly turned "off" and the pins go to the high-impedance state if the pin state specification bit in the standby control register (stbc:spl) is "1" when the device changes to stop or watch mode. ? to avoid current leakage, it is recommended to remain a known logic level of the input port pins during the standby mode. ? table 4.4-4 "port-3 pin state" lists the port-3 pin states.
144 chapter 4 i/o ports spl: pin state specification bit in the standby control register (stbc) hi-z: high impedance *: pin state of p30 is undetermined until the internal clock starts operation. table 4.4-4 port-3 pin state pin name normal operation main-sleep mode main-stop mode (spl=0) sub-sleep mode sub-stop mode (spl=0) watch mode (spl=0) main-stop mode (spl = 1) sub-stop mode (spl = 1) watch mode (spl = 1) reset p30/pwm1/bz cmos output /peripheral output hi-z "h"* p31/x0a p32/x1a general-purpose input/peripheral i/o input input
145 4.5 ports 4, 6 and 7 4.5 ports 4, 6 and 7 ports 4, 6, and 7 are output-only ports that also serve as the lcdc common and segment outputs. the output ports and lcdc segment (and common) outputs are selected as mask options. this section principally describes the port functions when operating as an output-only port. the section describes the port structure and pins, the pin block diagram, and the port register for port 4, 6, and 7. n structure of port 4, 6, and 7 ports 4 and 6 are each made up of three elements. ports 7 is made up of two elements. port 4: ? output-only pins/lcdc segment output pins (p40/seg0 to p47/seg7) ? port 4 data register (pdr4) port 6: ? output-only pins/lcdc segment output pins (p60/seg8 to p65/seg13) ? port 6 data register (pdr6) port 7: ? output-only pins/lcdc common output pins (p70/com2 to p71/com3) ? port 7 data register (pdr7) n port-4, 6, and 7 pins ports 4 consists of eight output-only pins of an n-ch open-drain output type, port 6 consists of six and port 7 consists of two. the pin functions are selected by mask options (mb89983) or by control register (mb89p985 and mb89pv980). when the lcdc common and segment outputs are selected. do not use these pins as output-only ports. port 4 option can be selected in eight-bit group and port 6 option can be selected in two-bit groups. table 4.5-1 "port-4, 6, and 7 pin" lists the port-4, 6,
146 chapter 4 i/o ports and 7 pins. *: the circuit type is "o" when lcdc segment output pin is selected. *1: hign current type reference: see section 1.7 "i/o pins and pin functions" for a description of the circuit type. see chapter 14 "lcd controller-driver" for details of pin operation when used as an lcdc common and segment outputs. n block diagram of port-4, 6 and 7 pin figure 4.5-1 block diagram of port-4, 6 and 7 for mb89983 table 4.5-1 port-4, 6, and 7 pin port pin name function shared peripheral i/o type circuit type input output mb89983 mb89p985 mb89pv980 port 4 p40/seg0 to p47/seg7*1 p40 to p47 output-only seg0 to seg7 lcdc segment output - n-ch open- drain n/o* s port 6 p60/seg8*1, p61/seg9*1, p62/seg10 to p65/seg13 p60 to p65 output-only seg8 to seg13 lcdc segment output port 7 p70/com2, p71/com3 p70, p71 output-only com2, com3 lcdc common output t/o* p-ch pdr (port data register) internal data bus pdr read output latch pdr write pin spl: pin state specification bit in the standby control register (stbc) n-ch stop, watch mode (spl = 1) mask option lcd common and segment output pull-up resistor (approx. 50 k /5.0 v) for p60 to p65 only p40 to p47
147 4.5 ports 4, 6 and 7 figure 4.5-2 block diagram of port-4, 6 and 7 for mb89p985 and mb89pv980 check: if you use port 4, 6 pins as the lcd common and segment output pins, do not set a pull-up resistor for those pins, and do not use the pins as output ports. n port-4, 6, and 7 registers port 4, 6, and 7 registers consist of pdr4, pdr6, and pdr7. each bit in these registers has a one-to-one relationship with a port 4,6, and 7 bit and pin respectively. table 4.5-2 "correspondence between pin and register for port 4, 6, and 7" shows the correspondence between the pins and register for port-4, 6, and 7. pdr (port data register) internal data bus pdr read output latch pdr write pin spl: pin state specification bit in the st andby control register (stbc) n-ch stop, watch mode (spl = 1) lcd common and segment output lcd control register 2 (lcr2) table 4.5-2 correspondence between pin and register for port 4, 6, and 7 port correspondence between register bit and pin port 4 pdr4 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 corresponding pin p47 p46 p45 p44 p43 p42 p41 p40 port 6 pdr6 - - bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 corresponding pin - - p65 p64 p63 p62 p61 p60 port 7 pdr7 ------bit 1bit 0 corresponding pin - - - - - - p71 p70
148 chapter 4 i/o ports 4.5.1 port-4, port-6, and port-7 registers (pdr4, pdr6, and pdr7) this section describes the port-4, port-6, and port-7 registers. n port-4, port-6, and port-7 register functions m port 4, port 6, and port 7 data registers (pdr4, pdr6, and pdr7) the pdr4, 6, and 7 registers hold the states of their respective output data latches. therefore, you cannot determine the pin states or lcdc common and segment output states by reading the registers. m settings as an lcdc common and segment output to use pins as lcdc common and segment outputs, that function must be selected by a mask option (mb89983) or by control register (mb89p985 and mb89pv980). the register bits for pins used for this purpose should be set to turn the output transistor "off" to prevent it from interfering with the lcdc common and segment output. table 4.5-3 "port-4, port-6, and port-7 register function" lists the functions of port-4, port-6, and port-7 register. table 4.5-3 port-4, port-6, and port-7 register function register data read write read/ write address initial value port 4 data register (pdr4) 0 output latch value is "0". sets "0" to the output latch. outputs an "l" level to the pin. r/w 000e h 11111111 b 1 output latch value is "1". sets "1" to the output latch. outputs an "h" level to the pin. port 4 data register (pdr4) 0 output latch value is "0". sets "0" to the output latch. outputs an "l" level to the pin. r/w 0012 h xx111111 b 1 output latch value is "1". sets "1" to the output latch. outputs an "h" level to the pin. port 4 data register (pdr4) 0 output latch value is "0". sets "0" to the output latch. outputs an "l" level to the pin. r/w 0013 h xxxxxx11 b 1 output latch value is "1". sets "1" to the output latch. outputs an "h" level to the pin.
149 4.5 ports 4, 6 and 7 r/w: readable and writable x: indeterminate *1: sets "0" to the output latch and turn the output transistor "on". *2: sets "1" to the output latch and turn the output transistor "off". pins with a pull-up resistor go to the pull-up state.
150 chapter 4 i/o ports 4.5.2 operation of port 4, port 6 and port 7 this section describes the operations of the port 4, port 6 and port 7. n operation of port 4, 6, and 7 m operation as an output port ? when used as an output-only port (mask option), the pins cannot be used for lcdc common and segment outputs. ? writing data to the pdr4, 6, and 7 register stores the data in the output latches. when the output latch value is "0" the output transistor turns "on" and an "l" level is output from the pin. when the output latch value is "1", the transistor turns "off" and the pin goes to the high-impedance state. for port 4 and 6 (mask option), if a pull-up is set to the output pin, the pin goes to the pull-up state when the output latch value is "1". ? reading the pdr4, 6, and 7 register always returns the output latch data. m operation as an lcdc common and segment output ? when the lcdc output option is selected, set the pdr4, 6, and 7-register bits corresponding to the lcdc common and segment output pins to "1" to turn the output transistor "off". ? you cannot read the lcdc output data by reading pdr4, 6 or 7. (if you read the pdr registers you will get the output latch data, not the lcdc output data.) m operation at reset resetting the cpu initializes the pdr4, 6, and 7 register values to "1". this turns "off" the output transistor for all pins and sets the pins to the high-impedance state. m operation in stop and watch modes the output transistors are forcibly turned "off" and the pins go to the high-impedance state if the pin state specification bit in the standby control register (stbc: spl) is "1" when the device changes to stop or watch mode.
151 4.5 ports 4, 6 and 7 table 4.5-4 "port-4, 6, and 7 pin state" lists the port-4, 6, and 7 pin states. note: pins with a pull-up resistor go to the "h" level (pull-up state) rather than to the high- impedance state when the output transistor is turned "off". table 4.5-4 port-4, 6, and 7 pin state pin name normal operation main-sleep mode main-stop mode (spl=0) sub-sleep mode sub-stop mode (spl=0) watch mode (spl=0) main-stop mode (spl = 1) sub-stop mode (spl = 1) watch mode (spl = 1) reset p40/seg0 to p47/seg7 output-only port/lcdc segment output hi-z* 1 hi-z* 2 p60/seg8 to p65/seg13 output-only port/lcdc segment output p70/com2, p71/com3 output-only port/lcdc common output *1: does not go to the high-impedance state when the pin is used as an lcdc common and segment output. *2: goes "l" when the pin is used as an lcdc common and segment output. spl: pin state specification bit in the standby control register (stbc) hi-z: high impedance
152 chapter 4 i/o ports 4.6 port 5 port 5 is an output-only port that also serves as an analog input. each pin can be switched between analog input and port operation in bit units. this section principally describes the port functions when operating as an output-only port. the section describes the port structure and pins, the pin block diagram, and the port register for port 5. n structure of port 5 port 5 consists of the following three components: ? output-only pins/analog input pins (p50/an0 to p53/an3) ? port-5 data register (pdr5) ? port 5 pull-up control register (purr5) (only available in mb89p985 and mb89pv980) n port-5 pins port 5 consists of four output pins of an n-ch open-drain output type. do not use these pins as output-only ports when the pins are used as the analog input for the a/d converter. table 4.6-1 "port-5 pin" lists the port-5 pins. reference: see section 1.7 "i/o pins and pin functions" for a description of the circuit type. see chapter 11 "a/d converter" for details of pin operation when used as an analog input. table 4.6-1 port-5 pin port pin name function shared peripheral i/o type circuit type input output mb89983 mb89p985 mb89pv980 port 5 p50/an0 p50 output-only an0 analog input 0 analog n-ch open- drain pq p51/an1 p51 output-only an1 analog input 1 p52/an2 p52 output-only an2 analog input 2 p53/an3 p53 output-only an3 analog input 3
153 4.6 port 5 n block diagram of port-5 pin figure 4.6-1 block diagram of port-5 for mb89983 figure 4.6-2 block diagram of port-5 for mb89p985 and mb89pv980 check: if using the a/d converter, do not set a pull-up resistor for any of p53/an3 to p50/an0. check: do not use the pins as output ports if using as an analog input. pdr (port data register) internal data bus pdr read output latch pdr writ e pin spl: pin state specification bit in the standby control register (stbc) n-ch stop, watch mode (spl = 1) p-ch a/d conver ter channel selector a/d converter analog input p-ch pull-up resistor (approx. 50 k /5.0 v) pdr (port data register) internal data bus pdr read output latch pdr write pin spl: pin state specification bit in the st andby control register (stbc) n-ch stop, watch mode (spl = 1) p-ch a/d converter channel selector a/d converter analog input p-ch pull up control register pull-up resistor (approx. 50 k /5.0 v)
154 chapter 4 i/o ports n port-5 registers the port-5 register consists of pdr5. each bit in the register has a one-to-one relationship with a port 5 pin. table 4.6-2 "correspondence between pin and register for port 5" shows the correspondence between the pins and register for port-5. table 4.6-2 correspondence between pin and register for port 5 port correspondence between register bit and pin port 5 pdr5, purr5 - - - - bit 3 bit 2 bit 1 bit 0 corresponding pin - - - - p53 p52 p51 p50
155 4.6 port 5 4.6.1 port-5 register (pdr5) this section describes the port-5 register. n port-5 register functions m port 5 data register (pdr5) the pdr5 register holds the output latch states. therefore, pin states cannot be checked by reading this register. m settings as an analog input when port 5 pins are used as analog signal inputs, write "1" to the corresponding bits of pdr5 to turn the output transistors "off". setting the pins to the high-impedance state. table 4.6-3 "port-4, port-6, and port-7 register function" lists the functions of the port-5 register. r/w: readable and writable *: pins with a pull-up resistor go to the pull-up state. m port 5 pull-up control registers (purr5) by using pull-up resistor option in each pin for port 5, setting is possible bit by bit when writing to pull-up control register for mb89p985 and mb89pv980 only. the pull-up resistor for mb89983 is selected by mask option. when pull-up resistor is selected in pull-up register in stop and clock mode (spl=1). the state of these pin are in "h" level (pull up state) rather than high impedance. however, during reset, pull up is unavailable and will be in high impedance state. figure 4.6-3 "pull up control registers setting (purr5)" is list of the pull-up resistor option setting of purr5 table 4.6-3 port-4, port-6, and port-7 register function register data read write read/ write address initial value port 5 data register (pdr5) 0 output latch value is "0". outputs an "l" level to the pin. (sets "0" to the output latch and turn the output transistor "on") r/w 000f h xxxx1111 b 1 output latch value is "1". sets the pin to the high- impedance state*. (sets "1" to the output latch and turn the output transistor "off.)
156 chapter 4 i/o ports figure 4.6-3 pull up control registers setting (purr5) note: for mb89p985 and mb89pv980, do not enabled the pull-up resistor when p50/an0 to p53/ an3 are used the a/d converter input. purr5 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0042 h pur53 pur52 pur51 pur50 ----1111 h rwr/wrwr/w pur53 pur52 pur51 pur50 0 p53 pull up on p52 pull up on p51 pull up on p50 pull up on 1 p53 pull up off p52 pull up off p51 pull up off p50 pull up off
157 4.6 port 5 4.6.2 operation of port 5 this section describes the operations of the port 5. n operation of port 5 m operation as an output port ? writing data to the pdr5 register stores the data in the output latch. when the output latch value is "0", the output transistor turns "on" and an "l" level is output from the pin. when the output latch value is "1", the transistor turns "off" and the pin goes to the high-impedance state. if a pull-up is provided the output pin the pin goes to the pull-up state when the output latch value is "1". ? reading the pdr5 register always returns the output latch value. m operation as an analog input ? set the pdr5 bit that corresponds to the analog input pin to "1" to turn the output transistor "off". ? reading the pdr5 register always returns the output latch value. m operation at reset resetting the cpu initializes the pdr5 register value to "1". this turns all the output transistors "off" and sets the pins to the high-impedance state. m operation in stop and watch modes the output transistors are forcibly turned "off" and the pins go to the high-impedance state if the pin state specification bit in the standby control register (stbc: spl) is "1" when the device changes to stop or watch mode. table 4.6-4 "port-5 pin state" lists the port-5 pin states. spl: pin state specification bit in the standby control register (stbc) hi-z: high impedance note: pins with a pull-up resistor go to the "h" level (pull-up state) rather than to the high- impedance state when the output transistor is turned "off". table 4.6-4 port-5 pin state pin name normal operation main-sleep mode main-stop mode (spl=0) sub-sleep mode sub-stop mode (spl=0) watch mode (spl=0) main-stop mode (spl = 1) sub-stop mode (spl = 1) watch mode (spl = 1) reset p50/an0 to p53/an3 output-only ports/analog input hi-z hi-z
158 chapter 4 i/o ports 4.7 program example for i/o ports this section gives an example program using the i/o ports. n program example for i/o ports m processing description ? port 0 and port 1 are used to illuminate all elements of seven segment led (eight segments if the decimal point is included). ? the p00 pin is used for the anode common pin of the led and the p10 to p17 pins operate as the segment pins. figure 4.7-1 "connection example for an eight segment led" shows the connection example for an eight segment led. figure 4.7-1 connection example for an eight segment led m coding example p10 p16 p17 p00 mb89980 series -- pdr0 equ 0000h ; address of the port 0 data register ddr0 equ 0001h ; address of the port 0 data direction register pdr1 equ 0002h ; address of the port 1 data register ddr1 equ 0003h ; address of the port 1 data direction register ;-------- main program ---------------------------------------------------------------------------------------------- cseg; [code segment] : clrb pdr0:0 ; set p00 to the "l" level. mov pdr1, #11111111b ; set all port-1 pins to the "h" level. mov pdr1, #11111111b ; set p00 as an output (#xxxxxxx1b).
159 4.7 program example for i/o ports mov pdr1, #11111111b ; set all port-1 pins as outputs. : ends ;-------- main program ---------------------------------------------------------------------------------------------- end
160 chapter 4 i/o ports
161 chapter 5 timebase timer this chapter describes the functions and operation of the timebase timer. 5.1 "overview of timebase timer" 5.2 "block diagram of timebase timer" 5.3 "timebase timer control register (tbtc)" 5.4 "timebase timer interrupt" 5.5 "operation of timebase timer" 5.6 "notes on using timebase timer" 5.7 "program example for timebase timer"
162 chapter 5 timebase timer 5.1 overview of timebase timer the timebase timer provides interval timer functions. four different interval times can be selected. the timebase timer uses a 21-bit free-run counter which counts-up in sync with the internal count clock (divide-by-two the main clock source oscillation). the timebase timer also provides the timer output for the oscillation stabilization delay time and the operating clock for the watchdog and timers. the timebase timer stops operating in modes in which the main clock master oscillator is stopped. n interval timer function the interval timer function generates repeated interrupts at fixed time intervals. ? the timer generates an interrupt each time the interval timer bit overflows on the timebase timer counter. ? the interval timer bit (interval time) can be selected from four different settings. table 5.1-1 "timebase timer interval time" lists the available interval for the timebase timer. f ch : main clock source oscillation the values enclosed in parentheses ( ) are for a 4.2 mhz main clock source oscillation. n clock supply function the clock supply function provides the timer output used for the main clock oscillation stabilization delay time (four values), and operation clock for some peripheral functions. table 5.1-2 "clocks supplied by timebase timer" lists the cycles of the clocks that the timebase timer supplies to various peripherals. table 5.1-1 timebase timer interval time internal count clock cycle interval time 2/fch (0.48 m s) 2 13 /f ch (approx. 1.95 ms) 2 15 /f ch (approx. 7.80 ms) 2 18 /f ch (approx. 62.4 ms) 2 22 /f ch (approx. 998.6 ms)
163 5.1 overview of timebase timer f ch : main clock source oscillation the values enclosed in parentheses ( ) are for a 4.2 mhz main clock source oscillation. note: the oscillation stabilization delay time should be used as a guide line since the oscillation cycle is unstable immediately after oscillation starts. table 5.1-2 clocks supplied by timebase timer clock destination clock cycle remarks main clock oscillation stabilization delay time 2 4 /f ch (approx. 0.0 ms) selected by the oscillator stabilization wait time select bit of the system clock control register (sycc: wt1, wt0), which is in the clock control section. 2 12 /f ch (approx. 0.98 ms) 2 16 /f ch (approx. 15.6 ms) 2 18 /f ch (approx. 62.4 ms) watchdog timer 2 22 /f ch (approx. 998.6 ms) count-up clock for the watchdog timer a/d converter 2 8 /f ch (approx. 61.0 m s) clock for continuous activation lcd controller/driver 2 7 /f ch (approx. 30.5 m s) frame cycle clock
164 chapter 5 timebase timer 5.2 block diagram of timebase timer the timebase timer consists of the following four blocks: ? timebase timer counter ? counter clear circuit ? interval timer selector ? timebase timer control register (tbtc) n block diagram of timebase timer figure 5.2-1 block diagram of timebase timer m timebase timer counter a 21-bit up-counter that uses the divide-by-two main clock source oscillation as a count clock. the counter stops when the main clock oscillator is stopped. m counter clear circuit in addition to being cleared by setting the tbtc register (tbr="0"), the counter is cleared when device changes to main stop (stbc: stp ="1") and subclock (sycc: scs="0") mode and by power-on reset (optional). tbof tbie tbc1 tbc0 tbc tbtc of of of timebase timer counter divide-by -two f ch watchdog timer clear power-on reset stop mode start irq7 timebase timer interrupt of: overflow f ch : main clock source oscillation counter clear circuit to a/d converter interval timer selector to watchdog timer to clock controller for the oscillation stabilization delay time selector to lcd controller/driver 2 1 2 2 2 3 . . . 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 . . . 2 21 of subclock mode start counter clear
165 5.2 block diagram of timebase timer m interval timer selector selects one of four operating timebase timer counter bits as the interval timer bit. an overflow on the selected bit triggers an interrupt. m tbtc register the tbtc register is used to select the interval timer bit, clear the counter, control interrupts, and check the state of the timebase timer.
166 chapter 5 timebase timer 5.3 timebase timer control register (tbtc) the timebase timer control register (tbtc) is used to select the interval times bit, clear the counter, control interrupts, and check the state of the timebase timer. n timebase timer control register (tbtc) figure 5.3-1 timebase timer control register (tbtc) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 000a h tbof tbie tbc1 tbc0 tbr 00---000b r/w r/w r/w r/w w tbr timebase timer initialization bit read write 0 clears timebase timer counter 1 reading always returns "1". no effect. the bit does not change. tbc1 tbc0 interval time selection bits 0 0 2 13 /f ch 01 2 15 /f ch 10 2 18 /f ch 11 2 22 /f ch f ch : main clock source oscillation tbie interrupt request enable bi t 0 disables interrupt request output. 1 enables int errupt output. tbof overflow interrupt request flag bit read write 0 no overflow on specified bit clears this bit. 1 overflow on specified bit no effect. the bit does not change. r/w :readable and writable w :write-only : unused x : indeterminate : i nitial value
167 5.3 timebase timer control register (tbtc) table 5.3-1 timebase timer control register (tbtc) bits bit function bit 7 tbof: overflow interrupt request flag bit ? this bit is set to "1" when count an overflow occurs on the specified bit of the timebase timer counter. ? an interrupt request is output when both this bit and the interrupt request enable bit (tbie) are "1". ? writing "0" clears this bit. writing "1" has no effect and does not change the bit value. bit 6 tbie: interrupt request this bit enables or disables an interrupt request output to the cpu. an interrupt request is output when both this bit and the overflow interrupt request flag bit (tbof) are "1". bit 5 bit 4 bit 3 unused bits ? the read value is indeterminate. ? writing to these bits has no effect on the operation. bit 2 bit 1 tbc1, tbc0: interval time selection bits these bits select the cycle of the interval timer. these bits select which bit of the timebase timer counter to use as the interval timer bit. four different interval times can be selected. bit 0 tbr: timebase timer initialization bit this bit clears the timebase timer counter. writing "0" to this bit clears the counter to "000000 h ". writing "1" has no effect and does not change the bit value. note: the read value is always "1".
168 chapter 5 timebase timer 5.4 timebase timer interrupt the timebase timer can generate an interrupt request when an overflow occurs on the specified bit of the timebase counter (for the interval timer function). n interrupts for interval timer function the counter counts-up on the internal count clock. when an overflow occurs on the selected interval timer bit, the overflow interrupt request flag bit (tbtc: tbof) is set to "1". at this time, an interrupt request (irq7) to the cpu is generated if the interrupt request enable bit is enabled (tbtc: tbie ="1"). write "0" to the tbof bit in the interrupt processing routine to clear the interrupt request. the tbof bit is set when at the specified counter bit overflows, regardless of the tbie bit value. check: when enabling an interrupt request output (tbie = "1") after wake-up from a reset, always clear the tbof bit (tbof = "0") at the same time. notes: an interrupt request is generated immediately if the tbof bit is "1" when the tbie bit is changed from disabled to enabled ("0" --> "1"). the tbof bit is not set if the counter is cleared (tbtc: tbr = "0") at the same time as an overflow on the specified bit occurs. n oscillation stabilization delay time and timebase timer interrupt if the interval time is set shorter than the main clock oscillation stabilization delay time, an interval interrupt request from the timebase timer (tbtc: tbof = "1") is generated at the time when the main clock mode starts operation. in this case, disable the timebase timer interrupt when changing to a mode in which the main clock oscillation is stopped (main stop mode and subclock mode). n register and vector table for timebase timer interrupts reference: see section 3.4.2 "interrupt processing" for details on the operation of interrupt. table 5.4-1 register and vector table for timebase timer interrupt interrupt interrupt level settings register vector table address register set bit upper lower irq7 ilr2(007d h ) l71 (bit 7) l70 (bit 6) ffec h ffed h
169 5.5 operation of timebase timer 5.5 operation of timebase timer the timebase timer has the interval timer function and the clock supply function for some peripherals. n operation of interval timer function (timebase timer) figure 5.5-1 "interval timer function settings" shows the settings required to operate the interval timer function. figure 5.5-1 interval timer function settings provided the main clock is oscillating, the timebase timer counter continues to count-up in sync with the internal count clock (divide-by-two main clock source oscillation). after being cleared (tbr = "0"), the counter restarts counting-up from zero. the timebase timer sets the overflow interrupt request flag bit (tbof) to "1" when an overflow occurs on the interval timer bit. consequently, the timebase timer generates interrupt requests at fixed intervals (the selected interval time), based on the time that the counter is cleared. n operation of clock supply function the timebase timer is also used as a timer to generate the main clock oscillation stabilization delay time. the time from when the timebase timer counter is cleared and starts counting-up until an overflow occurs on the oscillation stabilization delay time bit is the oscillation stabilization delay time. one of four possible delay times is selected by the oscillation stabilization delay time bits of the system clock control register (sycc: wt1, wt0). the timebase timer also provides the clock for the watchdog timer and buzzer output, a/d converter, and lcd controller/driver. clearing the timebase timer counter affects the operation of the continuous activation cycle of the a/d converter, the frame cycle of the lcd controller/ driver, and the buzzer output. if the timebase timer output is selected by the watchdog timer counter (wdtc: cs=0), it will also be cleared simultaneously. n operation of timebase timer the state of following operations are shown in figure 5.5-2 "operation of timebase timer". ? a power-on reset occurs. ? changes to sleep mode during operation of the interval timer function in the main clock mode. ? changes to main stop mode. ? a counter clear request occurs. the timebase timer is cleared by changing to subclock and main stop modes, and stops operation. the timebase timer counts the oscillation stabilization delay time after wake-up from subclock and main stop modes. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tbtc tbof tbie tbc1 tbc0 tbr 01 0 : used bit 1 : set "1". 0 : set "0".
170 chapter 5 timebase timer figure 5.5-2 operation of timebase timer counter value fffff h oscillation stabilization delay overflow 0000 h power-on reset (optional) cpu operation starts interval cycle (tbtc: tbc1, tbc0 = "11 h ") cleared by the interrupt processing routine. cleared by changing to main stop mode. counter clear (tbtc: tbr = "0") tbof bit tbie bit slp bit (stbc register) stp bit (stbc register) sleep mode wake-up from sleep mode by irq7 stop mode wake-up from stop mode by an external interrupt : indicates the oscillation stabilization delay time. for the case when the interval time selection bits in the timebase timer control register (tbtc: tbc1, tbc0) a re set to "11" (2 21 /f c ).
171 5.6 notes on using timebase timer 5.6 notes on using timebase timer this section lists points to note when using the timebase timer. n notes on using timebase timer m notes on setting bits by program the system cannot recover from interrupt processing if the overflow interrupt request flag bit (tbtc: tboc) is "1" and the interrupt request enable bit is enabled (tbtc: tbie = "1"). always clear the tbof bit. m clearing timebase timer in addition to being cleared by the timebase timer initialization bit (tbtc: tbr = "0"), the timer is cleared whenever the main clock oscillation stabilization delay time is required. when the timebase timer is selected as a count clock of the watchdog timer, clearing the timebase timer also clears the watchdog timer. m using as timer for oscillation stabilization delay time as the main clock source oscillation is stopped when the power is turned on during main-stop mode, and during subclock mode, the timebase timer provides the oscillation stabilization delay time after the oscillator starts. an appropriate oscillation stabilization delay time must be selected for the type of resonator connected to the main clock oscillator (clock generator). reference: see section 3.6.1 "clock generator section". m notes on peripheral functions that provided a clock supply from timebase timer in modes in which the main clock source oscillation is stopped, the timebase timer also stops, and the counter is cleared. as the clock derived from the timebase timer restarts output from its initial state when the timebase timer counter is cleared, the "h" level may be shorter or the "l" level longer by a maximum of half cycle. the clock of the watchdog timer also restarts output from its initial state. however, as the watchdog timer counter is cleared at the same time, the watchdog timer operates in normal cycle. figure 5.6-1 "effect on buzzer output of clearing timebase timer" shows the effect on the buzzer output of clearing the timebase timer.
172 chapter 5 timebase timer figure 5.6-1 effect on buzzer output of clearing timebase timer counter value 00fff h 00800 h 00000 h clock supplied to the buzzer output for the case when the buzzer selection bits in the buzzer register (bzcr: bz1, bz0) are set to "01 b ". (divide-by-8192 source oscillation, approximately 1.221 khz output at 10 mhz operation) clearing the counter by the program (tbtc: tbr = "0")
173 5.7 program example for timebase timer 5.7 program example for timebase timer this section gives a program example for the timebase timer. n program example for timebase timer m processing description ? generates repeated interval timer interrupts at 2 18 /f ch (f ch : the main clock source oscillation) intervals. at this time, the interval time is approximately 52.4 ms (at 4.2 mhz operation). m coding example tbtc equ 0000ah ; address of the timebase timer control register tbof equ tbtc:3 ; define the interrupt request flag bit. ilr2 equ 007eh ; address of the interrupt level setting register 2 int_v inq7 int_v dseg org dw ends abs 0ffech wari ; [data segment] ; set interrupt vector. ;-------- main program ---------------------------------------------------------------------------------------------- cseg : clri mov mov seti : ilr2,#01111111b tbtc,#00000100b ; [code segment] ; stack pointer (sp) etc. are already initialized. ; disable interrupts. ; set interrupt level (level 1). ; clear interrupt request flag enable interrupt request output, select 218/fc, and clear timebase timer. ; enable interrupts. ;-------- interrupt program------------------------------------------------------------------------------------------ wari clrb pushw xchw pushw : tbof a a,t a ; clear interrupt request flag. user processing
174 chapter 5 timebase timer : popw xchw popw reti ends a a,t a ;---------------------------------------------------------------------------------------------------- end
175 chapter 6 watchdog timer this chapter describes the functions and operation of the watchdog timer. 6.1 "overview of watchdog timer" 6.2 "block diagram of watchdog timer" 6.3 "watchdog timer control register (wdtc)" 6.4 "operation of watchdog timer" 6.5 "notes on using watchdog timer" 6.6 "program example for watchdog timer"
176 chapter 6 watchdog timer 6.1 overview of watchdog timer the watchdog timer is a 1-bit counter that uses, as its count clock source, either the timebase timer derived from the main clock, or the watch prescaler derived from the subclock. the watchdog timer resets the cpu if not cleared within a fixed time after activation. n watchdog timer function the watchdog timer is a counter provided to guard against program runaway. once activated, the counter must be repeatedly cleared within a fixed time interval. if the program becomes trapped in an endless loop or similar and does not clear the counter within the fixed time, the watchdog timer generates a four-instruction cycle watchdog reset to the cpu. either the timebase timer output or the watch prescaler output can be selected as the watchdog timer count clock. table 6.1-1 "watchdog timer interval time" lists the watchdog timer interval times. if not cleared, the watchdog timer generates a watchdog reset at a time between the minimum and maximum times listed. clear the counter within the minimum time given in the . reference: see section 6.4 "watchdog timer operation" for the details on the minimum and maximum time of the watchdog timer interval times. check: when the timebase timer output is selected as the watchdog timer counter count clock, the watchdog timer will be cleared at the same time (and each time) the timebase timer counter is cleared (tbtc: tbr = 0). when the timeclock prescaler is selected as the count clock, the watchdog timer will be cleared at the same time as the timeclock prescaler is cleared (wpcr: wclr = 0). therefore, if the counter selected as the count clock (either the timebase timer or the timeclock prescaler) is repeatedly cleared before the end of the watchdog timer interval, the watchdog timer will fail to perform its intended function. note: the watchdog timer counter is cleared whenever the device changes to sleep or stop watch mode. operation halts until the device returns to normal operation (run state). table 6.1-1 watchdog timer interval time count clock watch timer output (main clock oscillator frequency at 4.2 mhz) watch prescaler output (subclock oscillator frequency at 32.768 khz) minimum time approx. 998.6 ms* 1 500 ms* 2 maximum time approx. 1997.3 ms 1000 ms *1: divide-by-two the main clock source oscillation (f ch ) timebase timer count value (2 21 ). *2: the time of a clock cycle at the subclock oscillator frequency (f cl ) timeclock prescaler count (2 14 ).
177 6.2 block diagram of watchdog timer 6.2 block diagram of watchdog timer the watchdog timer consists of the following six blocks: ? count clock selector ? watchdog timer counter ? reset controller ? watchdog timer clear selector ? counter clear controller ? watchdog timer control register (wdtc) n block diagram of watchdog timer figure 6.2-1 block diagram of watchdog timer cs wte3 wte2 wte1 wte0 wdtc register counter clear watchdog timer 1-bit counter rst reset controller controller clear selector 2 22 /f ch (timebase timer output) 2 14 /f cl (watch prescaler output) count clock selector overflow watchdog timer start clear sleep mode start stop mode start watch mode start f ch : main clock source oscillation f cl : subclock sourc e oscillation clear signal from timebase timer clear signal from timeclock prescaler
178 chapter 6 watchdog timer m count clock selector the count clock selector selects the count clock for the watchdog timer counter. either the timebase timer counter output or the timeclock prescaler output can be selected as the count clock. m watchdog timer counter (1-bit counter) a 1-bit counter that uses the timebase timer output or the watch prescaler output as a count clock m reset controller generates a reset signal to the cpu when an overflow occurs on the watchdog timer counter. m watchdog timer clear selector the clear selector selects a watchdog timer clear signal from either the timebase timer or timeclock prescaler at the same time as the count clock selector selects a clock. (it selects the clear signal from the selected clock source.) m counter clear controller controls clearing and halting the operation of watchdog timer counter. m wdtc register the wdtc register is used to select the count clock, and to activate or clear the watchdog timer counter. as the register is write-only, the bit manipulation instructions cannot be used.
179 6.3 watchdog timer control register (wdtc) 6.3 watchdog timer control register (wdtc) the watchdog timer control register (wdtc) is used to activate or clear the watchdog timer. n watchdog timer control register (wdtc) figure 6.3-1 watchdog timer control register (wdtc) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0009 h cs wte3 wte2 wte1 wte0 0---xxxx a rw wwww wte3 wte2 wte1 wte0 watchdog timer control bits 0101 ? activate the watchdog timer (when writing for the first time after a reset). ? clear the watchdog timer (when writing for the second and subsequent times after a reset). other than the above no operation cs watchdog timer control bits 0 cycle time of timebase timer output (2 22 /f ch *1 ) 1 cycle time of watch prescaler output (2 14 /f cl *2 ) note: as the register is write-only, the bit manipulation instructions cannot be used. *1: f ch : main clock source oscillation *2: f cl : subclock source oscillation w : write-only : unused x : indeterminate : initial value
180 chapter 6 watchdog timer table 6.3-1 watchdog timer control register (wdtc) bits bit function bit 7 cs: count clock select bit ? at watchdog timer startup, selects the watchdog timer count clock. selects either the timebase timer output or the timeclock prescaler output as the count clock. note: when using the subclock mode, always select the timeclock prescaler output. make the count clock selection when the watchdog timer is started. once the timer is started, do not change the count clock. bit operation instructions cannot be used. bit 6 bit 5 bit 4 unused bits ? the read value is indeterminate. ? writing to these bits has no effect on operation. bit 3 bit 2 bit 1 bit 0 wte3, wte0: watchdog timer control bits ? writing "0101 b " to these bits activates (when writing for the first time after a reset) or clears (when writing for the second and subsequent times after a reset) the watchdog timer. ? writing a value other than "0101 b " has no effect on the operation. check: the read value is "1111 b " the bit manipulation instructions cannot be used.
181 6.4 operation of watchdog timer 6.4 operation of watchdog timer the watchdog timer generates a watchdog reset when the watchdog timer counter overflows. n operation of watchdog timer m activating watchdog timer ? the watchdog timer is activated by writing "0101 b " to the watchdog control bits in the watchdog control register (wdtc: wte3 to wte0) for the first time after a reset. the count clock select bit (wdtc: cs) is written to the desired state in the same write operation. ? once activated, the watchdog timer cannot be stopped other than by a reset. m clearing watchdog timer ? the watchdog timer counter is cleared by writing "0101 b "to the watchdog control bits in the watchdog control register (wdtc: wte3 to wte0) for the second or subsequent times after a reset. ? if the counter is not cleared within the interval time of the watchdog timer, the counter overflows and the watchdog timer generates an internal reset signal for four-instruction cycles. m interval time of watchdog timer the interval time changes depending on when the watchdog timer is cleared. figure 6.4-1 "watchdog timer clear and interval time" shows the relationship between the watchdog timer clear timing and the interval time. the indicated times apply if the timebase timer output is selected as the count clock, and the main clock source oscillation is 4.2 mhz.
182 chapter 6 watchdog timer figure 6.4-1 watchdog timer clear and interval time minimum time count clock output of the timebase timer watchdog clear overflow 1-bit watchdog counter watchdog reset maximum time watchdog clear overflow count clock output of the timebase timer 1-bit watchdog counter watchdog reset 998.6ms 1997.3 ms
183 6.5 notes on using watchdog timer 6.5 notes on using watchdog timer this section lists points to note when using the watchdog timer. n notes on using watchdog timer m stopping watchdog timer once activated, the watchdog timer can not stop until a reset generates. m count clock selection the only time the count clock select bit (wdtc: cs) can be changed is at watchdog timer activation. you can change it by writing the desired state to the count clock select bit (wdtc: cs) at the same time as you write "0101 b " to the watchdog control bits (wdtc: wte3 to wte0) to activate the watchdog timer. therefore, the cs bit cannot be changed by a bit operation instruction. do not change the cs bit after activating the timer. in the subclock mode, the main clock source oscillation is stopped, which means that the timebase timer also stops. for the watchdog timer to operate in subclock mode, then, the watch prescaler must have been selected in advance as the count clock (wdtc: cs = 1). m clearing watchdog timer ? clearing the counter being used as a count clock of the watchdog timer (timebase timer or watch prescaler) also simultaneously clears the watchdog timer counter. ? the watchdog timer counter is cleared on changing to sleep, stop or watch mode. m notes on programming when writing a program in which the watchdog timer is repeatedly cleared in the main loop, including interrupt processing, is less than the minimum watchdog timer interval time. m operation in subclock mode if the watchdog reset signal is generated in subclock mode, operation will start in main clock mode after an oscillation stabilization delay time. therefore, if the device has the reset signal output option, a reset signal will be output during the oscillation stabilization delay time.
184 chapter 6 watchdog timer 6.6 program example for watchdog timer this section gives a program example for the watchdog timer. n program example for watchdog timer m processing description ? selects the watch prescaler as the count clock and activates the watchdog timer immediately after the program. ? clears the watchdog timer in each loop of the main program. ? the processing time for the main loop, including interrupt processing, must be less than the minimum interval time of the watchdog timer (approximately 209.7 ms at 10 mhz operation). m coding example wdtc wdt_clr equ equ 00009h 10000101b ; address of the watchdog timer control register vect rst_v vect dseg org dw ends abs 0fffeh prog ; [data segment] ; set reset vector. ;-------- main program ---------------------------------------------------------------------------------------------- prog cseg mov w : ; [code segment] ; initialization routine after a reset ; set initial value of (for interrupt processing). initialization of peripheral functions (interrupts), etc. init : mov wdtc,#wdt_clr ; activate the watchdog timer. main mov : wdtc,#wdt_clr ; select the watch prescaler as the count clock. ; clear the watchdog timer. user processing (interrupt processing may occur during this cycle) : jmp main ; the loop must be executed in less than the minimum interval time of the watchdog timer. ends ;-------- main program ---------------------------------------------------------------------------------------------- end
185 chapter 7 8-bit pwm timer this chapter describes the functions and operation of the 8-bit pwm timer. 7.1 "overview of 8-bit pwm timer" 7.2 "block diagram of 8-bit pwm timer" 7.3 "structure of 8-bit pwm timer 1" 7.4 "structure of 8-bit pwm timer 2" 7.5 "8-bit pwm timer interrupts" 7.6 "operation of interval timer function" 7.7 "operation of pwm timer function" 7.8 "states in each mode during 8-bit pwm timer operation" 7.9 "notes on using 8-bit pwm timer" 7.10 "program example for 8-bit pwm timer"
186 chapter 7 8-bit pwm timer 7.1 overview of 8-bit pwm timer the 8-bit pwm timer can be selected to function as either an interval timer or pwm timer with 8-bit resolution. the interval timer function count-up in sync with either the 8/16-bit timer/counter (timer 1, timer 2) or one of three internal count clocks. therefore, an 8-bit interval timer time can be set and the output can be used to generate variable frequency square waves. also, the 8-bit pwm timer can be used as a d/a converter by connecting the pwm output to low pass filter. there are two 8-bit pwm timer "channels", that perform the same function: 8-bit pwm timer 1 and 8-bit pwm timer 2. n interval timer function (square wave output function) the interval timer function generates repeated interrupts at variable time intervals. also, as the 8-bit pwm timer can invert the output level of the pin (pwm1, pwm2) each time an interrupt is generated, the 8-bit pwm timer can output a variable frequency square waves. each 8-bit pwm timer (1 and 2) can operate independently of the other. ? the interval timer can operate with a cycle among 1 and 28 times the count clock cycle. ? the count clock can be selected from four different clocks. table 7.1-1 "interval time and square wave output range" lists the range for the interval time and square wave output. t inst : instruction cycle (affected by clock mode, etc.) t ext : 8/16-bit timer/counter timer 1 external clock period (8-bit pwm timer 1 only) 8-bit timer output cycle: 8/16-bit timer/counter 8-bit timer output (timer 1, timer 2) note: calculation example for the interval time and square wave frequency in this example, the main clock source oscillation (f ch ) is 4.2 mhz, the pwm compare register (comr) value is set to "dd h (221)" and the count clock cycle is set to 1 tinst. in this table 7.1-1 interval time and square wave output range count clock cycle interval time square wave output (hz) 1 internal count clock 1 t inst 1 t inst to 2 8 t inst 1/(2 t inst ) to 1/(2 9 t inst ) 216 t inst 2 4 t inst to 2 12 t inst 1/(2 5 t inst ) to 1/(2 13 t inst ) 364 t inst 2 6 t inst to 2 14 t inst 1/(2 7 t inst to 1/(2 15 t inst ) 48-bit timer output cycle 2 2 t inst to 2 10 t inst 2 2 t inst to 2 18 t inst 1/(2 3 t inst ) to 1/(2 19 t inst ) 2 6 t inst to 2 14 t inst 2 6 t inst to 2 22 t inst 1/(2 7 t inst ) to 1/(2 23 t inst ) 2 10 t inst to 2 18 t inst 2 10 t inst to 2 26 t inst 1/(2 11 t inst ) to 1/(2 27 t inst ) 1t ext to 2 8 t ext 1 t ext to 2 16 t ext 1/(2 t ext ) to 1/(2 9 t ext )
187 7.1 overview of 8-bit pwm timer case, the interval time and the frequency of the square wave output from the pwm1 or pwm2 pin (where the pwm timer operates continuously and the value of the comr register is constant) are calculated as follows. assume that the main clock mode (scs = 1) and its highest clock speed has been selected via the system clock control register (stcc: scs = 1, cs = 11 b , cs0 = 11 b , 1 instruction cycle = 4/f ch ). n pwm timer function the pwm timer function has 8-bit resolution and can control the "h" and "l" widths of one cycle. 8-bit pwm timers 1 and 2 can be operated independently of each other. ? as the resolution is 1/256, pulses can be output with duty ratios of between 0 and 99.6%. ? the cycle of the pwm wave can be selected from four types. ? the pwm timer can be used as a d/a converter by connecting the output to a low pass filter. table 7.1-2 "available pwm wave cycle for pwm timer function" lists the available pwm wave cycles for the pwm timer function. figure 7.1-1 "example d/a converter configuration using pwm output and low pass filter" shows an example d/a converter configuration. tinst: instruction cycle (affected by clock mode, etc.) tlext: 8/16-bit timer/counter timer 1 external clock period (8-bit pwm timer 1 only) 8-bit timer output cycle: 8/16-bit timer/counter 8-bit timer output (timer 1, timer 2) interval time = (1 4/f c ) (comr register value + 1) = (4/4.2 mhz) (221 + 1) = 211 m s output frequency = f ch /(1 8 (comr register value +1)) = 4.2 mhz/(8 (221 + 1)) = 2.4 khz table 7.1-2 available pwm wave cycle for pwm timer function 12 3 4 internal count clock 8-bit timer output cycle times count clock cycle 1 t inst 16 t inst 64 t inst 2 2 t inst to 2 10 t inst 2 6 t inst to 2 14 t inst 2 10 t inst to 2 18 t inst 1 t lext to 2 8 t ext pwm wave cycle 2 8 t inst 2 12 t inst 2 14 t inst 2 10 t inst to 2 18 t inst 2 14 t inst to 2 22 t inst 2 18 t inst to 2 26 t inst 2 8 t lext to 2 16 t ext
188 chapter 7 8-bit pwm timer figure 7.1-1 example d/a converter configuration using pwm output and low pass filter note: interrupt requests are not generated during operation of the pwm function. analog output waveform pwm output waveform pto pin pwm output r c analog output (va) tr va vcc th tl t va vcc 0 the relationship between the analog output voltage and pwm output waveform is: va/vcc = t h /t tr is the time taken for the output to stabilize.
189 7.2 block diagram of 8-bit pwm timer 7.2 block diagram of 8-bit pwm timer the 8-bit pwm timer consists of the following six blocks: ? count clock selector ? 8-bit counter ? comparator circuit ? pwm generator and output controller ? pwm compare register (comr) ? pwm control register (cntr) ? 8-bit pwm timer-1 and 8-bit pwm timer-2 have the same functions. n block diagram of 8-bit pwm timer figure 7.2-1 block diagram of 8-bit pwm timer p/tx p1 p0 tpe tir oe tie internal data bus comr1 pwm compare register irq9 start clk clear over flow 8-bit counter latch comparator circuit count clock selector x 1 x 16 x 64 pwm generator and output controller output pin p30/pwm1/bz output pin control bit 8-bit timer output 1 t inst timer/pwm note: the register and pin names listed first are for 8-bit pwm timer-1. the names enclosed in < > are for 8-bit pwm timer-2. cntr1 8 8 to1 t inst : instruction cycle. 8-bit timer output: timer 1 or timer 2 output (to1 or to2) of 8/16-bit timer/counter in 8-bit mode
190 chapter 7 8-bit pwm timer m count clock selector selects a count-up clock for the 8-bit counter from the three internal count clocks and the 8-bit timer output cycle of the 8/16-bit timer/counter. m 8-bit counter the 8-bit counter counts-up on the count clock selected by the count clock selector. m comparator circuit the comparator circuit has a latch to hold the comr register value. the circuit latches the comr register value when the 8-bit counter value is "00h". the comparator circuit compares the 8-bit counter value with the latched comr register value, and detects when a match occurs. m pwm generator and output controller when a match is detected during interval timer operation, an interrupt request is generated and, if the output pin control bit (cntr: oe) is "1", the output controller inverts the output level of the pwm1(pwm2) pin. at the same time, the 8-bit counter is cleared. when a match is detected during pwm timer operation, the pwm generator changes the output level of the pwm1(pwm2) pin from "h" to "l". the pin is set back to the "h" level when the next overflow occurs on the 8-bit counter. m comr register the comr register is used to set the value that is compared with the value of the 8-bit counter. m cntr register the cntr register is used to select the operating mode, enable or disable operation, set the count clock, control interrupts, and check the pwm status. setting the operation to pwm timer mode (p/tx = "0" disables clearing of the 8-bit counter and generation of interrupt requests (irq9, irqa) when the comparator circuit detects a match.
191 7.3 structure of 8-bit pwm timer 1 7.3 structure of 8-bit pwm timer 1 this section describes the pin, pin block diagram, register source, and interrupts of the 8-bit pwm timer. n 8-bit pwm timer 1 pin the 8-bit pwm timer uses the p30/pwm1/bz pin. this pin can function as a output-only port (p30), or buzzer output/bz, or as the interval timer or pwm timer output (pwm1). pwm1: when the interval timer function is selected, the square waves are output to this pin. when the pwm timer function is selected, the pin outputs the pwm wave. setting the output pin control bit (cntr1: oe) to "1" makes pin p30/pwm1/bz the output- only pin for 8-bit pwm timer 1. once this has been done, the pin performs its pwm1 function regardless of the state of the port data register output latch data (pdr3: bit 0) and buzzer output. n block diagram of 8-bit pwm timer pin figure 7.3-1 block diagram of 8-bit pwm timer pin pdr (port data register) internal data bus pdr read output latch pdr write pin spl: pin state specification bit in the standby control register (stbc) n-ch p-ch stop, watch mode (spl = 1) p30/pwm1/bz pwm1 pwm1 output enable output buzzer buzzer output enable output
192 chapter 7 8-bit pwm timer n 8-bit pwm timer 1 registers figure 7.3-2 8-bit pwm1 timer registers check: as the pwm1 compare register (comr1) is write-only, the bit manipulation instructions can be used. n 8-bit pwm timer 1 interrupt source irq9: for the interval timer function, the 8-bit pwm timer generates an interrupt request if interrupt request output is enabled (cntr: tie = "1") when the counter value matches the value set in the comr register. (no interrupt requests are generated when the pwm function is operating.) cntr1 (pwm1 control register) comr1 (pwm1 compare register) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 001e h p/tx p1 p0 tpe tir oe tie 0-000000 b r/w r/w r/w r/w r/w r/w r/w address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 001f h xxxxxxxx b wwwwwwww r/w: readable and writable w : write-only : unused x : indeterminate
193 7.3 structure of 8-bit pwm timer 1 7.3.1 pwm1 control register (cntr1) the pwm1 control register (cntr1) is used to select the operating mode of the 8-bit pwm timer (interval timer operation or pwm timer operation), enable or disable operation, select the count clock, control interrupts, and check the state of the 8-bit pwm timer. n pwm1 control register (cntr1) figure 7.3-3 pwm1 control register (cntr 1) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 001e h p/tx p1 p0 tpe tir oe tie 0-000000 b r/w r/w r/w r/w r/w r/w r/w tie interrupt request enable bit 0 disables interrupt request output. 1 enables interrupt request output. oe output pin control bit 0 functions as a general-purpose port (p30) or buzzer output. 1 functions as the interval timer/pwm timer output pin (pwm1). tir interrupt request flag bit read write interval timer function pwm timer function 0 counter value and set value do not match. no change clears this bit. 1 counter value and set value match. no effect. the bit does not change. tpe counter operation enable bit 0 stops count operation. 1 starts count operation. p1 p0 clock selection bits 0 0 internal count clock 1 t inst *1 01 16 t inst *1 10 64 t inst *1 11 timer 1 output *2 p/tx operatin g mode selection bit 0 operates as an interval timer. 1 operates as a pwm timer. *1 : t inst : instruction cycle *2 : the timer 1 output referred to here is the timer 1 output cycle when the 8/16-bit timer/ counter is used in the 8-bit mode r/w : readable and writable r : read-only w : write-only : unused x : indeterminate : initial value
194 chapter 7 8-bit pwm timer table 7.3-1 pwm 1 control register (cntr1) bit bit function bit 7 p/tx: operating mode selection bit ? this bit switches between the interval timer function (p/ tx = "0") and pwm timer function (p/tx = "1"). check: write to this bit when the counter operation is stopped (tpe = "0"), interrupts are disabled (tie = "0"), and the interrupt request flag bit is cleared (tir = "0"). bit 6 unused bit ? the read value is indeterminate. ? writing to this bit has no effect on the operation. bit 5 bit 4 p1, p0: clock selection bit ? these bits select the count clock for the interval timer function and pwm timer function. ? these bits can select the count clock from three internal count clocks or the output cycle of the timer 1. ? if the timer 1 output is selected, operate the 8/16-bit timer/counter in 8-bit mode. check: do not change p1 and p0 when the counter is operating (tpe = "1"). bit 3 tpe: counter operation enable bit ? this bit activates or stops operation of the pwm timer function and interval timer function. ? writing "1" to this bit starts the count operation. writing "0" to this bit stops the count and clears the counter to "00 h ". bit 2 tir: interrupt request flag bit ? for the interval timer function: this bit is set to "1" when the counter and pwm 1 compare register (comr1) values match. an interrupt request is output to the cpu when both this bit and the interrupt request enable bit (tie) are "1". ? for the pwm timer function: interrupt requests are not generated. ? writing "0" clears this bit. writing "1" has no effect and does not change the bit value. bit 1 oe: output pin control bit ? the p30/pwm1/bz pin functions as a general-purpose port (p30) or buzzer output when this bit is set to "0" and a dedicated pin (pwm1) when this bit is set to "1". ? the pwm1 pin outputs a square wave when the interval timer function is selected and a pwm waveform when the pwm timer function is selected. bit 0 tie: interrupt request enable bit this bit enables or disables and an interrupt request output to the cpu. an interrupt request is output when both this bit and the interrupt request flag bit (tir) are "1".
195 7.3 structure of 8-bit pwm timer 1 7.3.2 pwm 1 compare register (comr1) the pwm 1 compare register (comr1) sets the interval time for the interval timer function. the register value sets the "h" width of the pulse for the pwm timer function. n pwm 1 compare register (comr1) figure 7.3-4 "pwm 1 compare register (comr1)" shows the bit structure of the pwm1 compare register. as the register is write-only, bit manipulation instructions cannot be used. figure 7.3-4 pwm 1 compare register (comr1) m interval timer operation this register is used to set the value to be compared with the counter value. the register specifies the interval time. the counter is cleared when the counter value matches the value set in this register, and the interrupt request flag bit is set to "1" (cntr 1: tir = "1"). if data is written to the comr1 register during counter operation, the new value applies from the next cycle (after the next match is detected). note: the comr1 setting for interval timer operation can be calculated using the following formula. the instruction cycle time is affected by the clock mode, and the speed-shift selection. comr 1 register value = interval time/(count clock cycle instruction cycle) - 1 m pwm timer operation this register is used to set the value to be compared with the counter value. the register therefore sets the "h" width of the pulse. the pwm1 pin outputs an "h" level until the counter value matches the value set in this register. from the match until the counter value overflows, the pwm1 pin outputs an "l" level. if data is written to the comr 1 register during counter operation, the new value applies from the next cycle (after the next overflow). address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 001f h xxxxxxxx b wwwwwwww w: write-only x: indeterminate
196 chapter 7 8-bit pwm timer note: in pwm timer operation, the comr1 setting and the pwm cycle time can be calculated using the following formulas. (the instruction cycle time is affected by the clock mode, and the speed-shift selection.) comr1 register value = duty ratio (%) 256 pwm wave cycle = count clock cycle instruction cycle 256
197 7.4 structure of 8-bit pwm timer 2 7.4 structure of 8-bit pwm timer 2 this section describes the pin, pin block diagram, register source, and interrupts of the 8-bit pwm timer. n 8-bit pwm timer 2 pin the 8-bit pwm timer 2 uses the p27/pwm2 pin. this pin can function either as a general- purpose i/o port (p27) or as the interval timer or pwm timer output (n-ch open-drain output)(pwm2). pwm2: when the interval timer function is selected, the square waves are output to this pin. when the pwm timer function is selected, the pin outputs the pwm wave. setting the p27/pwm2 pin as a dedicated pin in the output pin control bit (cntr 2: oe = "1") automatically sets the pin as an output pin, regardless of the port data direction register (ddr2: bit 7) value, and sets the pin to function as the pwm2 pin. n block diagram of 8-bit pwm timer 2 pin figure 7.4-1 block diagram of 8-bit pwm timer 2 pin for mb89983 note: pins with a pull-up resistor (optional) go to the "h" level during a reset or in stop and watch modes. pdr (port data register) ddr internal data bus pdr read pdr read (for bit manipulation instructions) output latch pdr write ddr write pin spl: pin state specification bit in the standby control register (stbc) n-ch stop, watch mode (spl = 1) (port data direction register) timer output timer output enable stop, watch mode high current drive-type output pull-up resistor (approx. 50 k /5.0 v) r p27/pwm2
198 chapter 7 8-bit pwm timer figure 7.4-2 block diagram of 8-bit pwm timer 2 pin for mb89p985 and mb89pv980 n 8-bit pwm timer 2 registers figure 7.4-3 8-bit pwm timer 2 registers check: as the pwm2 compare register (comr2) is write-only, the bit manipulation instructions cannot be used. n 8-bit pwm timer 2 interrupt source irqa: for the interval timer function, the 8-bit pwm timer generates an interrupt request if interrupt request output is enabled (cntr 2: tie = "1") when the counter value matches the value set in the comr2 register. (no interrupt requests are generated when the pwm function is operating.) pdr (port da ta register) ddr internal data bus pdr read pdr read (for bit manipulation instr uctions) output latch pdr write ddr write pin spl: pin state specification bit in the standby control register (s tbc) n-ch stop, watch mode (spl = 1) (port data direction register) timer output timerl output enable stop, watch mode high current drive-type outputs p27/pwm2 cntr2 (pwm2 control register) comr2 (pwm2 compare register) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0020 h p/tx p1 p0 tpe tir oe tie 0-000000 b r/w r/w r/w r/w r/w r/w r/w address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0021 h xxxxxxxx b wwwwwwww r/w: readable and writable w : write-only : unused x : indeterminate
199 7.4 structure of 8-bit pwm timer 2 7.4.1 pwm 2 control register (cntr2) the pwm 2 control register (cntr2) is used to select the operating mode of the 8-bit pwm timer (interval timer operation or pwm timer operation), enable or disable operation, select the count clock, control interrupts, and check the state of the 8-bit pwm timer. n pwm 2 control register (cntr2) figure 7.4-4 pwm 2 control register (cntr2) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0020 h p/tx p1 p0 tpe tir oe tie 0-000000 b r/w r/w r/w r/w r/w r/w r/w tie interrupt request enable bit 0 disables interrupt request output. 1 enables interrupt request output. oe output pin control bit 0 function as a general-purpose port (p27). 1 function as the interval timer/pwm timer output pin (pwm2). ti r interrupt request flag bit read write interval timer function pwm timer function 0 counter value and set value do not match. no change clears this bit. 1 counter value and set value match. no effect. the bit does not change. tpe counter operation enable bit 0 stops count operation. 1 starts count operation. p1 p0 clock selection bits 0 0 internal count clock 1 t inst *1 01 16 t inst *1 10 64 t inst *1 11 timer 2 output *2 p/tx operating mode selecti on bit 0 operates as an int erval timer. 1 operates as a pwm timer. *1 : t inst : instruction cycle *2 : the timer 1 output referred to here is the timer 1 output cycle when the 8/16-bit tim er/ counter is used in the 8-bit mode r/w : readable and writable r : read-only w : write-only : unused x : indeterminate : initial value
200 chapter 7 8-bit pwm timer table 7.4-1 pwm 2 control register (cntr2) bits bit function bit 7 p/tx: operating mode selection bit ? this bit switches between the interval timer function (p/ tx = "0") and pwm timer function (p/tx = "1") check: write to this bit when the counter operation is stopped (tpe = "0"), interrupts are disabled (tie = "0"), and the interrupt request flag bit is cleared (tir = "0"). bit 6 unused bit ? the read value is indeterminate. ? writing to this bit has no effect on the operation. bit 5 bit 4 p1, p0: clock selection bit ? these bits select the count clock for the interval timer function and pwm timer function. ? selects either one of three internal count clock, or the timer 2 output cycle. ? when you selects the timer 2 output, operate the 8/16- bit timer/counter in its 8-bit mode. check: do not change p1 and p0 when the counter is operating (tpe = "1"). bit 3 tpe: counter operation enable bit ? this bit activates or stops operation of the pwm timer function and interval timer function. ? writing "1" to this bit starts the count operation. writing "0" to this bit stops the count and clears the counter to "00 h ". bit 2 tir: interrupt request flag bit ? for the interval timer function: this bit is set to "1" when the counter and pwm 2 compare register (comr2) values match. an interrupt request is output to the cpu when both this bit and the interrupt request enable bit (tie) are "1". ? for the pwm timer function: interrupt requests are not generated. ? writing "0" clears this bit. writing "1" has no effect and does not change the bit value. bit 1 oe: output pin control bit ? the p27/pwm2 pin functions as a general-purpose port (p27) when this bit is set to "0" and a dedicated pin (pwm2) when this bit is set to "1". ? the pwm2 pin outputs a square wave when the interval timer function is selected and a pwm waveform when the pwm timer function is selected. bit 0 tie: interrupt request enable bit this bit enables or disables and an interrupt request output to the cpu. an interrupt request is output when both this bit and the interrupt request flag bit (tir) are "1".
201 7.4 structure of 8-bit pwm timer 2 7.4.2 pwm 2 compare register (comr2) the pwm 2 compare register (comr2) sets the interval time for the interval timer function. the register value sets the "h" width of the pulse for the pwm timer function. n pwm 2 compare register (comr2) figure 7.4-5 "pwm2 compare register (comr2)" shows the bit structure of the pwm 2 compare register. as the register is write-only, bit manipulation instructions cannot be used. figure 7.4-5 pwm2 compare register (comr2) m interval timer operation this register is used to set the value to be compared with the counter value. the register specifies the interval time. the counter is cleared when the counter value matches the value set in this register, and the interrupt request flag bit is set to "1" (cntr2: tir = "1"). if data is written to the comr2 register during counter operation, the new value applies from the next cycle (after the next match is detected). note: the comr2 setting for interval timer operation can be calculated using the following formula. (the instruction cycle time is affected by the clock mode, and the speed-shift selection.) comr2 register value = interval time/(count clock cycle instruction cycle) - 1 m pwm timer operation this register is used to set the value to be compared with the counter value. the register therefore sets the "h" width of the pulse. the pwm2 pin outputs an "h" level until the counter value matches the value set in this register. from the match until the counter value overflows, the pwm2 pin outputs an "l" level. if data is written to the comr2 register during counter operation, the new value applies from the next cycle (after the next overflow). address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0021 h xxxxxxxx b wwwwwwww w: write-only x: indeterminate
202 chapter 7 8-bit pwm timer note: in pwm timer operation, the comr2 setting and the pwm cycle time can be calculated using the following formulas. (the instruction cycle time is affected by the clock mode, and the speed-shift selection.) comr2 register value = duty ratio (%) 256 pwm wave cycle = count clock cycle instruction cycle 256
203 7.5 8-bit pwm timer interrupts 7.5 8-bit pwm timer interrupts the 8-bit pwm timer can generate an interrupt request when a match is detected between the counter value and pwm compare register value for the interval timer function. interrupt requests are not generated for the pwm timer function. 8-bit pwm timer-1 generates the irq9 as an interrupt request and 8-bit pwm timer-2 generates the irqa as an interrupt request. n interrupts for interval timer function the counter value is counted-up from "00 h " on the selected count clock. when the counter value matches the pwm compare register (comr) value, the interrupt request flag bit (cntr: tir) is set to "1". at this time, an interrupt request (irq9, irqa) to the cpu is generated if the interrupt request enable bit is enabled (cntr: tie = "1"). write "0" to the tir bit in the interrupt processing routine to clear the interrupt request. the tir bit is set to "1" when the counter value matches the set value, regardless of the value of the tie bit. note: the tir bit is not set if the counter is stopped (cntr: tpe = "0") at the same time as the counter value matches the comr register value. an interrupt request is generated immediately if the tir bit is "1" when the tie bit is changed from disabled to enabled ("0" --> "1"). n registers and vector tables for 8-bit pwm timer interrupts reference: see section 3.4.2 "interrupt processing" for details on the interrupt operation. table 7.5-1 registers and vector tables for 8-bit pwm timer interrupts interrupt interrupt level setting register vector table address register setting bits upper lower 8-bit pwm timer 1 irq9 ilr3 (007e h ) l91 (bit3) l90 (bit2) fff8 h fff9 h 8-bit pwm timer 2 irqa ilr3 (007e h ) la1 (bit5) la0 (bit4) fff6 h fff7 h
204 chapter 7 8-bit pwm timer 7.6 operation of interval timer function this section describes the operation of the timer interval timer function of the 8-bit pwm timer. n operation of interval timer function figure 7.6-1 "interval timer function settings" shows the settings required to operate as an interval timer function. figure 7.6-1 interval timer function settings on activation, the counter starts counting-up from "00 h " on the rising edge of the selected count clock. when the counter value matches the value set in the comr register (compare value), the pwm timer inverts the level of the output pin (pwm1, pwm2) on the next rising edge of the count clock, clears the counter, sets the interrupt request flag bit (cntr: tir = "1"), and restarts counting from "00 h ". figure 7.6-2 "operation of 8-bit pwm timer" shows the operation of the 8-bit pwm timer. figure 7.6-2 operation of 8-bit pwm timer bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cntr p/tx p1 p0 tpe tir oe tie 0 comr sets interval time (compare value). : used bit 1 : set "1". 0 : set "0". 1 counter value compare value (ff h ) compare value (80 h ) ff h 80 h 00 h comr value (ff h ) timer cycle comr value modified (ff h ? 80 h )* cleared by the program time tir bit tpe bit oe bit pwm pin when the output pin control bit (oe) is "0", the pin operates as a general-purpose i/o port (p30 or p27). *: if the pwm compare register (comr) value is modified during counter operation, the new value is used from the next cycle.
205 7.6 operation of interval timer function check: do not change the count clock cycle (cntr: p1, p0) during operation of the interval timer function (cntr: tpe = "1"). notes: setting the comr register value to "00 h " causes the pwm pin output to be inverted with the cycle of the selected count clock. when the counter is stopped (cntr: tpe = "0") while the interval timer function is selected, the pwm pin outputs an "l" level.
206 chapter 7 8-bit pwm timer 7.7 operation of pwm timer function this section describes the operation of the pwm timer function of the 8-bit pwm timer. n operation of pwm timer function figure 7.7-1 "pwm timer function settings" shows the settings required to operate as the pwm timer function. figure 7.7-1 pwm timer function settings on activation, the counter starts counting-up from "00 h " on the rising edge of the selected count clock. the pwm pin (pwm1, pwm2) outputs (pwm waveform) an "h" level until the counter value matches the value set in the comr register. from the match until the counter value overflows (ff h --> 00 h ), the pto pin outputs an"l" level. figure 7.7-2 "example of pwm waveform output (pto pin)" shows the pwm waveforms output from the pto pin. figure 7.7-2 example of pwm waveform output (pto pin) check: do not change the count clock cycle (cntr: p1, p0) during operation of the pwm timer function (cntr: tpe = "1"). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cntr p/tx p1 p0 tpe tir oe tie 1 comr sets h width of pulse (compare value). : used bit : unused bit 1 : set "1". 1 1 for comr register value of "00 h " (duty ratio = 0%) counter value 00 h h l h l h l 00 h 00 h counter value counter value pwm waveform pwm wavef orm pwm waveform for comr register value of "80 h " (duty ratio = 50%) for comr register value of "ff h " (duty ratio = 99.6%) ff h 00 h ff h 00 h ff h 00 h 80 h one count width width
207 7.7 operation of pwm timer function note: when the pwm timer function is selected, the pwm pin maintains its existing level when the counter is stopped (cntr: tpe = "0").
208 chapter 7 8-bit pwm timer 7.8 states in each mode during 8-bit pwm timer operation this section describes the operation of the 8-bit pwm timer when the device changes to sleep or stop mode or an operation halt request occurs during operation. n operation during standby mode or operation halt figure 7.8-1 "counter operation during standby modes or operation halt (for interval timer function)" and 7.8-2 "operation during standby modes or operation halt (for pwm timer function)" show the counter value states when the device changes to sleep or stop mode, or an operation halt request occurs, during operation of the interval timer function or pwm timer function. the counter halts and maintains its current value when the device changes to stop mode. operation starts again from the stored counter value after wake-up from stop mode by an external interrupt. therefore, the first interval time or pwm wave cycle does not match the set value. always initialize the 8-bit pwm timer after wake-up from stop mode. m for interval timer function figure 7.8-1 counter operation during standby modes or operation halt (for interval timer function) counter value comr value (ff h ) ff h 00 h timer cycle time tir bit tpe bit pto pin slp bit cleared by the program stop request oscillation stabilization delay time cleared by the operation halt. operation halts operation restarts (oe = "1") (stbc register) stp bit (stbc register) sleep mode wake-up from sleep mode by irq9 or irqa. "l" while conter is stopped. * stop mode wake-up from stop mode by an external interrupt. * : the pwm pin (pwm1, pwm2) goes to the high-impedance state during stop mode if the pin state specification bit in the standby control register (stbc: spl) is "1" and the pwm pin is not set to with a pull- up resistor (unless the pin is pulled up, a pull-up option selectable for the pwm2 pin only). when the spl bit is "0", the pin maintains its value prior to changing to stop mode.
209 7.8 states in each mode during 8-bit pwm timer operation m for pwm timer function figure 7.8-2 operation during standby modes or operation halt (for pwm timer function) * pto pin (pwm waveform) tpe bit slp bit (stbc register) stp bit (stbc register) sleep mode wake-up from sleep mode by an interrupt other than irq9 and irqa (irq9 and irqa are not generated). operation halts maintains the level prior to halting. operation restarts oscillation stabilization delay time wake-up from stop mode by an external interrupt. * : the pwm pin (pwm1, pwm2) goes to the high-impedance state during stop mode if the pin state specification bit in the standby control register (stbc: spl) is "1" and the pwm pin is not set to with a pull-up resistor (unless the pin is pulled, a pull-up option selectable for the pwm2 pin only). when the spl bit is "0", the pin maintains its value prior to changing to stop mode. 00 h 00 h 00 h 00 h 00 h stop mode
210 chapter 7 8-bit pwm timer 7.9 notes on using 8-bit pwm timer this section lists points to note when using the 8-bit pwm timer. n notes on using 8-bit pwm timer m error activating the counter by program is not synchronized with the start of counting-up using the selected count clock. therefore, the time from activating the counter until a match with the pwm compare register (comr) is detected may be shorter than the theoretical time by a maximum of one cycle of the count clock. figure 7.9-1 "error on starting counter operation" shows the error that occurs on starting counter operation. figure 7.9-1 error on starting counter operation m notes on setting by program ? do not change the count clock cycle (cntr: p1, p0) when the interval timer function or pwm timer function is operating (cntr: tpe = "1"). ? stop the counter (cntr: tpe = "0"), disable interrupts (tie = "0"), and clear the interrupt request flag (tir = "0") before switching between the interval timer function and pwm timer function (cntr: p/tx). ? interrupt processing cannot return if the interrupt request flag bit (cntr: tir) is "1" and the interrupt request enable bit is enabled (cntr: tie = "1"). always clear the tir bit. ? the tir bit is not set if the counter is disabled (tpe = "0") at the same time as the counter and comr register values match. m notes when using 8/16-bit timer/counter output ? when selecting timer 1 output for 8-bit pwm timer 1 and operating the 8/16-bit timer/counter in 16-bit ode, always select internal count clock for 8-bit pwm timer 2. timer 2 output cannot be selected. counter value count clock one cycle error cycle for 00 h counter activate 00 h 01 h 02 h 03 h 04 h
211 7.10 program example for 8-bit pwm timer 7.10 program example for 8-bit pwm timer this section gives program examples for the 8-bit pwm timer. n program example for interval timer function m processing description ? generates repeated interval timer interrupts at 5 ms intervals. ? outputs a square wave to the pwm1 pin that inverts after each interval time. ? with a main clock master oscillation f ch of 4.2 mhz, and the highest speed clock selected by the speed-shift function (1 instruction cycle time = 4/f ch ), the comr register is set for an interval time of approximately 5 ms. (an internal clock period of 64 tinst is selected as the count clock.) the comr register setting is calculated as follows: comr register value = 5 ms/(64 4/4.2 mhz) - 1 = 81.0 (051h) m coding example cntr1 comr1 equ equ 001eh 001fh ; address of the pwm 1 control register ; address of the pwm 1 compare register tpe tir equ equ cntr1:3 cntr1:2 ; define the counter operation enable bit. ; define the interrupt request flag bit. ilr3 equ 007eh ; address of the interrupt level setting register 3 int_v irq9 int_v dseg org dw ends abs 0ffe8h wari ; [data segment] ; set reset vector. ;-------- main program ---------------------------------------------------------------------------------------------- cseg : clri clrb mov mov mov seti : tpe ilr3,#11110111b comr1,#051h cntr1,#00101011b ; [code segment] ; stack pointer (sp) etc. are already initialized. ; disable interrupts. ; stop counter operation. ; set interrupt level (level 1). ; value compared with the counter value (interval time) ; operate interval timer, select 64 tinst, start counter operation, clear interrupt request flag, enable to pin output, enable interrupt request output. ; enable interrupts.
212 chapter 7 8-bit pwm timer n program example for pwm timer function m processing description m coding example ;-------- interrupt program ------------------------------------------------------------------------------------------ -- wari clrb pushw xchw pushw : tir a a,t a ; clear interrupt request flag. ; save a and t. user processing : popw xchw popw reti ends a a, t a ; restore a and t. ;--------------------------------------------------------------------------------------------------------------------------- end ? generates a pwm wave with a duty ratio of 50%. then, changes the duty ratio to 25%. ? does not generate interrupts. ? for a 4.2 mhz source oscillation, (f ch ), and the highest speed clock selected by the speedshift function (1 instruction cycle time = 4/f ch ), selecting the interval 16 t inst gives a pwm wave cycle of 16 4/4.2 mhz 256 3.901 ms. ? the following shows the comr register value required for a duty ratio of 50%: comr register value = 50/100 256 = 128 (080 h ) count clock cntr1 comr1 equ equ 001eh 001fh ; address of the pwm 1 control register ; address of the pwm 1 compare register tpe equ cntr1:3 ; define the counter operation enable bit. ;-------- main program ---------------------------------------------------------------------------------------------- cseg : clrb mov mov tpe comr1,#80h cntr1,#100110101b ; [code segment] ; stop counter operation. ; set "h" width of pulse. duty ratio = 50% ; operate pwm timer, select 16 t inst , start counter operation, clear interrupt request flag, enable to pin output, and disable interrupt request output.
213 7.10 program example for 8-bit pwm timer : : mov : ends comr1,#40h ; change the duty ratio to 25% (effective from the next pwm wave cycle). ;--------------------------------------------------------------------------------------------------------------------------- end
214 chapter 7 8-bit pwm timer
215 chapter 8 8/16-bit timer/counter this chapter describes the functions and operation of the 8/16-bit timer/counter. 8.1 "overview of 8/16-bit timer/counter" 8.2 "block diagram of 8/16-bit timer/counter" 8.3 "structure of 8/16-bit timer/counter" 8.4 "8/16-bit timer/counter interrupt" 8.5 "operation of interval timer function" 8.6 "operation of counter function" 8.7 "operation of the square wave output initial setting function" 8.8 "operation of 8/16-bit timer/counter stop and restart" 8.9 "states in each mode during 8/16-bit timer/counter operation" 8.10 "notes on using 8/16-bit timer/counter" 8.11 "program examples for 8/16-bit timer/counter"
216 chapter 8 8/16-bit timer/counter 8.1 overview of 8/16 -bit timer/counter the 8/16-bit timer/counter is made up of two 8-bit timers (timer 1 and timer 2) that can be used separately (8-bit mode) or connected in cascade to form one counter (16-bit mode). timer 1 can be selected to function as either an interval timer or a counter. the interval timer function counts up in sync with one of three interval count clocks. the counter function counts up by a clock input to the external pin.the output can be used to generate variable frequency square wave output. timer 2 functions as an interval timer clocked by one of three internal count clocks. in the 16 bit mode, it is connected in series with timer 1. n interval timer function the interval timer function generates repeated interrupts at variable intervals. also, as the 8/16- bit timer/counter can invert the output level of the pin (to pin) each time an interval time is generated, the 8/16-bit timer/counter can output variable frequency square waves (timer 1 in 8 bit mode, or 16 bit mode). ? in 8-bit mode, timer 1 and timer 2 operate as two independent interval timers, each of which can count time intervals ranging from the clock period (the time of one clock cycle) to 2 8 times the clock period. ? in 16-bit mode, the two counters form a single 16-bit timer, with timer 1 containing the lsbs and timer 2 the msbs. the interval timer can operate with a cycle among 1 and 2 16 times the internal count clock cycle. ? the count clock can be selected from three different internal clocks. (an external clock can be selected for timer 1, but it will then function as a counter). ? timer 1 and timer 2 outputs can be used as the count clocks for 8-bit pwm timer 1 and 8- bit pwm timer 2, respectively. ? the timer 1 output can be used as the clock for the a/d converter in continuous operation mode. table 8.1-1 "timer 1 interval times and square wave frequencies in 8-bit mode" to 8.1-3 "interval times and square wave frequencies 16-bit mode" list the interval time and square wave output ranges for the various modes. table 8.1-1 timer 1 interval times and square wave frequencies in 8-bit mode count clock cycle interval time square wave output range (hz) internal count clock 2 t inst 2 t inst to 2 9 t inst 1/(2 2 t inst ) to 1/(2 10 t inst ) 32 t inst 2 5 t inst to 2 13 t inst 1/(2 6 t inst ) to 1/(2 14 t inst ) 512 t inst 2 9 t inst to 2 17 t inst 1/(2 10 t inst ) to 1/(2 18 t inst ) external clock 1 t ext 1 t ext to 2 8 t ext 1/(2 t ext ) to 1/(2 9 t ext )
217 8.1 overview of 8/16 -bit timer/counter t inst : instruction cycle (affected by clock mode, etc.) t ext : external clock period note: calculation example for the interval time and square wave frequency: in this example, the main clock source oscillation (f ch ) is 4.2 mhz, the timer 1 data register (t1dr) value is set to "dd h (221)" and the count clock cycle is set to the 8-bit mode operation at 2 tinst. in this case, the timer 1 interval time and frequency of square wave output from the to pin (where the pwm timer operates continuously and the value of the t1dr register is constant) are calculated as follows. assume that the main clock mode (scs = 1) and the highest clock speed (cs1/cs0 = 11 b ) has been selected via the system clock control register (sycc: scs = 1, cs1 = 11 b , cs0 = 11 b ) (1 instruction cycle = 4/f ch ). table 8.1-2 timer 2 interval times and square wave frequencies in 8-bit mode count clock cycle interval time square wave output range (hz) internal count clock 2 t inst 2 t inst to 2 9 t inst 1/(2 2 t inst ) to 1/(2 10 t inst ) 32 t inst 2 5 t inst to 2 13 t inst 1/(2 6 t inst ) to 1/(2 14 t inst ) 512 t inst 2 9 t inst to 2 17 t inst 1/(2 10 t inst ) to 1/(2 18 t inst ) external clock 1 t ext 1 t ext to 2 8 t ext 1/(2 t ext ) to 1/(2 9 t ext ) table 8.1-3 interval times and square wave frequencies 16-bit mode count clock cycle interval time square wave output range (hz) internal count clock 2 t inst 2 t inst to 2 17 t inst 1/(2 2 t inst ) to 1/(2 18 t inst ) 32 t inst 2 5 t inst to 2 21 t inst 1/(2 6 t inst ) to 1/(2 22 t inst ) 512 t inst 2 9 t inst to 2 25 t inst 1/(2 10 t inst ) to 1/(2 26 t inst ) external clock 1 t ext 1 t ext to 2 16 t ext 1/(2 t ext ) to 1/(2 17 t ext ) interval time = (2 4/f ch ) (t1dr register value + 1) = (8/4.2 mhz) (221 + 1) 422.9 s output frequency = f ch /(2 8 (t1dr register value + 1)) = 4.2 mhz/ (16 (221 + 1)) 1.18 khz
218 chapter 8 8/16-bit timer/counter n counter function the counter function counts rising edges of an external count clock applied to the external pin (ec pin). since the external clock can be selected only for timer 1, the counter function operates in either the 8-bit timer 1 or 16 bit mode. ? the counter counts up, clocked by external clocks. when the count equals the set value, it generates an interrupt request and inverts the level being output at the to pin. ? in the 8 bit mode, timer 1 can count as high as 2 8 . ? in the 16 bit mode, the function counts as high as 2 16 . ? by injecting an external clock having a set period, the counter function can be used the same way as the interval timer function.
219 8.2 block diagram of 8/16-bit timer/counter 8.2 block diagram of 8/16-bit timer/counter the 8/16-bit timer/counter consists of the following five blocks: ? count clock selectors 1 and 2 ? counter circuits 1 and 2 ? square wave output controller ? timer data registers (t1dr and t2dr) ? timer control registers (t1cr and t2cr) n block diagram of 8/16-bit timer/counter figure 8.2-1 block diagram 8/16-bit timer/counter t inst : instruction cycle t1str t1stp t1cs0 t1cs1 t1os0 t1os1 t1ie t1if t1cr t2str t2stp t2cs0 t2cs1 t2os0 t2os1 t2ie t2if t2cr t.ff / 2 r,s ck q p22/to to1 to2 t.ff 2 / q ck 1t inst 2 32 512 1t inst 2 32 512 p20/ec / 2 ck clr co eq load load eq ck clr square wave output controller initialize pin control/output output enable signal interrupt request irq5 pin count clock selector 1 count clock selector 2 counter circuit 1 counter circuit 2 8-bit counter t1dr read internal data bus comparator comparison data latch data register data register comparison data latch comparator 8-bit counter pin t1dr and t2dr write t1dr read
220 chapter 8 8/16-bit timer/counter m count clock selectors 1, 2 this circuit selects an input clock. in the 8-bit timer 1 and 16 bit modes, count clock selector 1 selects one of four clocks: three internal clocks, and an external clock. in the 8-bit mode, count clock selector 2 selects one of three internal clocks only. m counter circuit 1, 2 counter circuit 1 and counter circuit 2 are each made up of an 8-bit counter, a comparator, a comparison data latch, and a data register (t1dr or t2dr). in each counter circuit, the 8-bit counter is an up-counter clocked by the selected count clock. the comparator compares the count in the counter with the value in the comparison data latch. when it detects a match, it clears the counter, and loads the contents of the data register into the comparison data latch. in the 8 bit-mode, the two counter circuits operate independently as timer 1 and timer 2. in the 16-bit mode, the two circuits are connected in series to form a single 16-bit counter with counter circuit 1 forming the low (8 lsbs) end of the counter, and counter circuit 2 at the high (8 msbs) end. m square wave output control circuit an interrupt request is generated when the comparator detects a match in the 8-bit timer 1 mode or the 16-bit mode. at this time, if the square wave output is enabled, the output control circuit inverts the level output at the to pin. the circuit can also initialize the output level to have the output square wave start out in a specific state ("h" or "l"). m t1dr and t2dr registers the value to be compared with the count in the counter is set by writing the desired value into these registers. they can be read to determine the current counter values. m t1cr and t2cr registers the t1cr and t2cr registers are used to select the function, to enable or disable operation, control interrupts, and check the timer/counter status.
221 8.3 structure of 8/16-bit timer/counter 8.3 structure of 8/16-bit timer/counter this section describes the pins, pin block diagram, registers, and interrupt source of the 8/16-bit timer/counter. n 8/16-bit timer/counter pins the 8/16-bit timer/counter uses the p20/ec and p22/to pins. the p20/ec pin can function either as a general-purpose i/o port (p20), as the external clock input pin of timer (ec). the p22/to pin can function either as general-purpose i/o port (p22), as the square wave output pin of time (to). ec: in the 8-bit timer 1 or 16-bit mode, if external clock input (counter function) is selected (t1cr: t1cs1 = 11 b , t1cs0 = 11 b ), the counter counts the external clocks applied to this pin. the p20/ec pin sets the pin as an input port in the port data direction register ddr2: bit 0 = "0" when using as the ec pin. to: in the 8-bit timer 1 or 16-bit mode, a square wave is output at this pin. enabling square wave output (t1cr: t1os1, t1os0 = expect 00 b ) automatically sets the p22/to pin as an output pin, regardless of the port data direction register (ddr2: bit 2) value, and sets the pin to function as the to pin. n block diagram of 8/16-bit timer counter pins figure 8.3-1 block diagram of 8/16-bit timer/counter pins for mb89983 pdr (port data register) ddr internal data bus pdr read pdr read (for bit manipulation instructions) output latch pdr write ddr write pin spl: pin state specification bit in the standby control register (stbc) n-ch stop, watch mode (spl = 1) to peripheral input ec pin only (port data direction register) to pin only stop, watch mode pull-up resistor (approx. 50 k /5.0 v) r p20/ec p22/to timer output output enable signal
222 chapter 8 8/16-bit timer/counter figure 8.3-2 block diagram of 8/16-bit timer/counter pins for mb89p985 and mb89pv980 note: pins with a pull-up resistor (optional) go to the "h" level during a reset or in stop mode and watch mode (spl = "1"). pdr (port data register) ddr internal data bus pdr read pdr read (for bit manipulation instructions) output latch pdr write ddr write pin spl: pin state specification bit in the standby control register (stbc) n-ch stop, watch mode (spl = 1) to peripheral input ec pin only (port data direction register) to pin only stop, watch mode p20/ec p22/to timer output output enable signal
223 8.3 structure of 8/16-bit timer/counter n 8/16-bit timer/counter registers figure 8.3-3 8/16-bit timer/counter registers n 8/16-bit timer/counter interrupt source irq5: in the interval timer and counter functions, if the interrupt request output is enabled, an irq5 interrupt request will be generated when the count in the counter equals the value set in the data register. interrupt request outputs are enabled by setting the proper timer control register bit (t1cr: t1ie = 1 in the 8-bit timer 1 or 16-bit mode; or t2cr: t2ie = 1 in the 8-bit timer 2 mode). t1cr (timer 1 control register) t2cr (timer 2 control register) t1dr (timer 1 data register) t2dr (timer 2 data register) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0019h t1if t1ie t1os1 t1os0 t1cs1 ts1cs0 t1stp t1str x000xxx0 b r/w r/w r/w r/w r/w r/w r/w r/w address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0018h t2if t2ie t2os1 t2os0 t2cs1 t2cs0 t2stp t2str x000xxx0 b r/w r/w r/w r/w r/w r/w r/w r/w address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 001bh xxxxxxxx b r/w r/w r/w r/w r/w r/w r/w r/w address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 001ah xxxxxxxx b r/w r/w r/w r/w r/w r/w r/w r/w r/w: readable and writable x : indeterminate
224 chapter 8 8/16-bit timer/counter 8.3.1 timer 1 control register (t1cr) in the 8-bit timer 1 and in the 16-bit mode, the timer 1 control register (t1cr) is used to select functions, to enable/disable operation, to control interrupts, and to check status. in the 8-bit mode, the timer 2 control register (t2cr) must still be initialized, even when only timer 1 is used. n timer 1 control register (t1cr) figure 8.3-4 pwc pulse width control register 1 (t1cr) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0019 h t1if t1ie t1os1 t1os0 t1cs1 t1cs0 t1stp t1str x000xxx0 b r/w r/w r/w r/w r/w r/w r/w r/w t1str timer activation bit 0 stops counter 1 clears counter, then starts it t1stp timer stop bits 0 causes counter to resume counting without clearing 1 temp orarily stops counter t1cs1 t1cs0 count clock selection bits 00 2 t inst 01 32 t inst 10 512 t inst 11 external clock t1os1 t1os0 square wave output control bits 0 0 use pin for general-purpose port (p22) 01 set the initial value of output square wave as "l" state 10 set the initial value of output square wave as "h" state 11 output set level at square wave output pin (to).* t1ie interrupt request enable bit 0 disable interrupt request output 1 enable interrupt request outp ut t1if interrupt request flag bit read write 0 no counter match clears this bit 1 have counter match no effect: the bit does not change. t inst : instruction cycle *: the square wave output pin will go to the level corresponding to data set when t1str is 0. r/w : readable and writable w : write only : unused bit x : indeterminate : initial value
225 8.3 structure of 8/16-bit timer/counter table 8.3-1 timer 1 control register (t1cr) bits bit function bit 7 t1if: interrupt request flag bit ? 8 bit-mode: ? set to "1" when the count in the timer 1 counter matches the value set in the t1dr, the timer 1 data register (comparison data latch). ? 16-bit mode: ? set to "1" when the counts in the timer 1 and timer 2 counters match the values set in the t1dr and t2dr registers, respectively. ? an interrupt request is output when both this bit and the interrupt request enable bit (t1ie) are "1". ? writing "0" clears this bit. writing "1" has no effect and does not change the bit value. bit 6 t1ie: interrupt request enable bit ? this bit enables or disables an interrupt request output to the cpu. ? an interrupt request is output when both this bit and the interrupt request flag bit (t1if) are "1". bit 5 bit 4 t1os1 and t1os0: square wave output control bits ? p22/to is a general-purpose i/o port pin (p22) if both of these bits are "00b". if either bit is "1", it is the square wave output pin (to). ? if written to "01b", or "10b", the initialize data will be set in the square wave output controller, but the corresponding level will not be output to the to pin. ? if both bits are "11b", and the function is in the stop timer state (t1str= 0), the to pin is set to a level corresponding to the initialize data. bit 3 bit 2 t1cs1 and t1cs0: clock source selection bits ? selects the count clock to be supplied to the counter. ? selects one of three internal clocks, or an external clock. ? when both bits are "11b", timer 1 operates as a counter with the external clock is selected as the count clock. check: if external clock input is selected (t1cs1, t1cs0 = 11b), p20/ec must be set as an input port. bit 1 t1stp: timer stop bit ? this bit is used to temporarily stop the counter. ? writing this bit to "1" temporarily stops the counter. writing it to "0" when the timer in startup state (t1str = 1), restarts the counter where it left off. bit 0 1str: timer activation bit ? starts and stops timer. ? changing this bit from "0" to "1" clears the counter. at this time, if the timer is in the continuous operation mode (t1stp = 0), the counter starts (counts up, clocked by the selected count clock). writing this bit to "0" stops the counter. ? in the 16 bit mode, both timer 1 and timer 2 are cleared at timer start (t1stp = 0 --> 1).
226 chapter 8 8/16-bit timer/counter check: before using 8/16-bit timer/counter timer 1 only in 8 bit mode, first set the timer count clock selection bits of the timer 2 control register (t2cr: t2cs1, t2cs0) to some state other than "11 b ". operating in this mode without making this register setting could result in faulty operation. remark: the square wave output pin, to1 will be unknown at the time from setting the initial value of square wave output by t1os0, t1os1 ("01 b " or "10 b " to setting output to to1( t1os0, t1os1= "11 b ").
227 8.3 structure of 8/16-bit timer/counter 8.3.2 timer 2 control register (t2cr) in the 8 bit mode, the timer 2 control register (t2cr) is used to select functions, to enable/disable operation, to control interrupts, and to check states. in the 16 bit mode, although the function is controlled by the timer 1 control register (t1cr), the timer 2 control register (t2cr) must still be set. n timer 2 control register (t2cr) figure 8.3-5 timer 2 control register (t2cr) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0018 h t2if t2ie t2os1 t2os0 t2cs1 t2cs0 t2stp t2str x000xxx0 b r/w r/w r/w r/w r/w r/w r/w r/w t2str timer activation bit 0 stops counter 1 clears counter, then starts it t2stp timer stop bit 0 causes counter to resume counting without clearing 1 temporarily stops counter t2cs1 t2cs0 count clock selection bits 00 2 t inst 01 32 t inst 10 512 t inst 11 16-bit mode t2os1 t2os0 unused bits 0 0 always write to "00". 01 prohibited setting 10 prohibited setting 11 prohibited setting t2ie interrupt request enable bit 0 disables interrupt request output 1 enables interrupt request output t2if interrupt request flag bit read write 0 no counter match clears this file 1 have counter match no effect: the bit does not change. r/w : readable and writable w : write-only : unused x : indeterminate : initial value
228 chapter 8 8/16-bit timer/counter check: when using timer 2 in the 16-bit mode, set t2cs1 and t2cs0 to "11b"; then use the t1cr register to control the circuit. table 8.3-2 timer 2 control register (t2cr) bits bit function bit 7 t2if: interrupt request flag bit ? set to "1" when the count in the timer 2 counter matches the value set in the t2dr, the timer 2 data register (comparison data latch). ? an interrupt request is output when both this bit and the interrupt request enable bit (t2ie) are "1". ? writing "0" clears this bit. writing "1"has no effect and does not change the bit value. check: in the 16-bit mode, the t1if bit is the valid interrupt request flag, and the t2if bit has no effect. bit 6 t2ie: interrupt request enable bit ? this bit enables or disables an interrupt request output to the cpu. ? an interrupt request is output when both this bit and the interrupt request flag bit (t2if) are "1". check: in the 16 bit mode, the t1ie bit is the valid interrupt request enable bit, and the t2ie bit has no effect. bit 5 bit 4 t2os1 and t2os0: unused bits these bits are not used in timer 2. they should always be written to "00". bit 3 bit 2 t2cs1 and t2cs0: clock source selection bits ? tselects the count clock to be supplied to the counter. ? selects one of three internal clocks. ? setting to "11b" selects the 16-bit mode. check: in 16-bit mode, t1cs1 and t1cs0 select the clock. t2cs1 and t2cs0 serve only to select the 16 bit-mode. bit 1 t2stp: timer stop bit ? this bit is used to temporarily stop the counter. ? writing this bit to "1" temporarily stops the counter. writing it to "0" when the timer start bit (t2str) is "1", restarts the counter where it left off. check: in 16-bit mode, t1stp is the stop bit, and t2stp has no effect. bit 0 t2str: timer activation bit ? starts and stops timer. ? changing this bit from "0" to "1" clears the counter. at this time, if the t2stp bit is "0", the counter starts (counts up, clocked by selected count clock). writing this bit to "0" stops the counter. check: in 16-bit mode, t1str is the start bit, and t2str has no effect.
229 8.3 structure of 8/16-bit timer/counter 8.3.3 timer 1 data register (t1dr) the timer 1 data register (t1dr) is used to set all or part of the interval time or counter value, and to read out all or part of the counter value, depending on the mode and function being used. in 8-bit mode, it sets the timer 1 interval time (interval timer function) or counter value (counter function), and reads out the counter value. in 16-bit mode, it sets the 8 lsbs of the 16-bit timer interval (interval timer function) or counter value (counter function), and reads out the counter value. n timer 1 data register (t1dr) the value set into this register is compared with the counter value (count). if you read the register, you get the current counter value. the register setting cannot be read out. figure 8.3-6 "timer 1 data register (t1dr)" shows the bit structure of the timer 1 data register. figure 8.3-6 timer 1 data register (t1dr) m 8-bit mode (timer 1) the value in this register is compared with the count in the timer 1 counter. for the interval timer function it sets the interval time, and for the counter function, it sets the count to be detected. when count operation enabled (t1cr: t1str = 0 --> 1, t1stp = 0), the value in the t1dr register is loaded into the comparison data latch, and the counter starts counting up. when the counter counts up to where it matches the value in the comparison data latch, the value in the t1dr register is re-loaded into the comparison data latch, and the counter is cleared and continues to count. since the comparison data latch is reloaded when a match is detected, if a new value is loaded into the t1dr register while the counter is counting, the new value will not take effect until the next count cycle (after a match is detected in the current cycle). note: the t1dr setting for interval timer operation can be calculated using the following formula. (the instruction cycle time is affected by the clock mode, and the speed-shift selection.) t1dr register value = interval time/(count clock cycle instruction cycle) -1 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 001b h xxxxxxxxa r/w r/w r/w r/w r/w r/w r/w r/w r/w: readable and writable
230 chapter 8 8/16-bit timer/counter m 16-bit mode the value in this register is compared with the counter value for the lower 8 bits . (lsbs) of the 16-bit timer. in the interval timer function, this sets the lower 8 bits of the interval time setting, and in the counter function, the lower 8 bits of the count to be detected. the contents of the t1dr register are loaded into the lower 8 bits of the comparison data latch when the counter first starts operating and when a match is detected in the 16-bit count. therefore, if a new value is loaded into the t1dr register while the 16-bit counter is counting, the new value will not take effect until after the next match is detected. reference: for information on t1dr settings in the interval timer mode, refer to section 8.3.4 "timer 2 data register (t2dr)".
231 8.3 structure of 8/16-bit timer/counter 8.3.4 timer 2 data register (t1dr) the timer 2 data register (t2dr) is used to set all or part of the interval time or counter value, and to read out all or part of the counter value, depending on the mode and function being used. in 8-bit mode, it sets the timer 2 interval time (interval timer function) or counter value (counter function), and reads out the counter value. in 16- bit mode, it sets the 8 msbs of the 16-bit timer interval (interval timer function) or counter value (counter function), and reads out the counter value. n timer 2 data register (t2dr) the value set into this register is compared with the counter value (count). if you read the register, you get the current counter value. the register setting cannot be read out. figure 8.3-7 "timer 2 data register (t2dr)" shows the bit structure of the timer 2 data register. figure 8.3-7 timer 2 data register (t2dr) m 8-bit mode (timer 2) the value in this register is compared with the count in the timer 2 counter. for the interval timer function, it sets the interval time, and for the counter function, it sets the count to be detected. the value in the t2dr register is reloaded into the comparison data latch when counter operation starts, and when a match is detected. if a new value is loaded into the t2dr register while the counter is counting, the new value will not take effect until the next count cycle (after a match is detected in the current cycle). note: the t2dr setting for interval timer operation can be calculated using the following formula. (the instruction cycle time is affected by the clock mode, and the speed-shift selection.) t2dr register value = interval time/(count clock cycle instruction cycle time) -1 m 16-bit mode the value in this register is compared with upper 8 bits (msbs) of the 16-bit timer. in the interval timer function, this sets the upper 8 bits of the interval time setting, and in the counter function, the upper 8 bits of the count to be detected. the contents of the t2dr register are loaded into the upper 8 bits of the comparison data latch when the counter first starts operating and when a match is detected in the 16-bit count. therefore, if a new value is loaded into the t2dr register while the 16-bit counter is counting, the new value will not take effect until after the next match is detected. in the 16 bit mode, the operation of the counter is controlled by the timer 1 control register (t1cr). address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 001a h xxxxxxxx b r/w r/w r/w r/w r/w r/w r/w r/w r/w: readable and writable
232 chapter 8 8/16-bit timer/counter note: in the interval timer function, the t1dr and t2dr register settings can be calculated from the following formula. (the instruction cycle time is affected by the clock mode, and the speed-shift selection.) 16-bit data value = interval time/(count clock cycle instruction cycle) -1 the 8 msbs of the 16-bit data value are the t2dr setting, and the 8 lsbs are the t1dr setting.
233 8.4 8/16-bit timer/counter interrupt 8.4 8/16-bit timer/counter interrupt in the 8/16-bit timer/counter, interrupt conditions are satisfied (if interrupts are enabled) when the counter matches the data register. this is true for both the interval timer and counter functions. n 8/16-bit timer/counter interrupt table 8.4-1 "8/16-bit timer/counter interrupt control bits and interrupts" lists the 8/16-bit timer/ counter interrupts, interrupt request flags and irq output enable bits. in 8-bit mode, 8/16-bit timer/counter interrupt requests are generated independently for timer 1 and timer 2. in 16-bit mode, the interrupt request is generated only for timer 1, but basic operation is the same. interrupt operation will therefore be described only for timer 1 in 8-bit mode. m 8-bit mode timer 1 interrupt operation the counter counts up from "00h" clocked by the selected count clock. when the count in the counter matches the value in the comparison data latch (corresponding to the value in timer data register t1dr), the interrupt request flag bit is set to "1" (t1cr: t1if). at this time, an interrupt request (irq5) to the cpu is generated if the interrupt request enable bit is enabled (t1cr: t1if="1"). write "0" to the tcef bit in the interrupt processing routine to clear the interrupt request. the t1if bit is set to "1" when the counter value matches the set value, regardless of the value of the t1ie bit. in 8 bit mode, although timer 1 and timer 2 operate independently of each other, they both generate irq5. when processing irq5, then, the software may have to check the interrupt request flag bits to determine which timer generated the interrupt. note: the t1if bit is not set if the counter is stopped (t1cr: t1str = "0" at the same time as the counter value matches the t1dr register. an interrupt request is generated immediately if the t1if bit is "1" when the t1ie bit is changed from disabled to enabled ("0" --> "1"). table 8.4-1 8/16-bit timer/counter interrupt control bits and interrupts 8-bit mode 16-bit mode timer 1 timer 2 timer 1+timer2 interrupt request flag bit t1cr:t1if t2cr:t2if t1cr:t1if interrupt request enable bit t1cr:t1ie t2cr:t2ie t1cr:t1ie interrupt source 8-bit counter matches t1dr 8-bit counter matches t2dr 16-bit counter matches t1dr+t2dr
234 chapter 8 8/16-bit timer/counter n registers and vector table for 8/16-bit timer/counter interrupt reference: see section 3.4.2 "interrupt processing" for details on the interrupt operation. table 8.4-2 registers and vector table for 8/16-bit timer/counter interrupt interrupt interrupt level settings register vector table address register setting bits upper lower irq5 ilr2 (007dh) l51 (bit 3) l50 (bit 2) fff0 h fff1 h
235 8.5 operation of interval timer function 8.5 operation of interval timer function this section describes the operation of the interval timer function of the 8/16-bit timer/ counter. n operation of interval timer function m 8-bit mode figure 8.5-1 "interval timer function (timer 1) settings" shows the settings required to operate timer 1 as the interval timer function in the 8-bit mode. figure 8.5-1 interval timer function (timer 1) settings figure 8.5-2 "interval timer function (timer 2) settings" shows the settings required to operate timer 2 as the interval timer function in the 8-bit mode. figure 8.5-2 interval timer function (timer 2) settings on activation in 8-bit mode, the counter starts counting-up from "00 h " on the rising edge of the selected count clock. eventually, the count in the counter will match the value set in the data register (comparison data latch). when this occurs, the timer control register interrupt request flag bit (t1cr: t1if) is set to "1" and the counter starts counting-up again from "00 h ". if using timer 1, the output of the square wave output control circuit is inverted when a match is detected; and if square wave output is enabled (t1cr: t1os1, t1os0 = values other than "00 b ", a square wave is output at the to pin. figure 8.5-3 "operation of interval timer (timer 1)" shows the interval timer function operation in the 8 bit mode. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t1cr t1if t1ie t1os1 t1os0 t1cs1 t1cs0 t1s tp t1str t1dr sets the interval time (compare value). t2cr t2if t2ie t2os1 t2os0 t2cs1 t2cs0 t2stp t2str 00 : used bit : unused bit 0 : set "0". other than "11" other than "11" bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t2cr t2if t2ie t2os1 t2os0 t2cs1 t2cs0 t2stp t2str 00 t2dr sets the interval time (compare value). : used bit 0 : set "0". other than "11"
236 chapter 8 8/16-bit timer/counter figure 8.5-3 operation of interval timer (timer 1) m 16-bit mode figure 8.5-4 "interval timer function settings (16-bit mode)" shows the settings required to operate the interval timer function in the 16-bit mode. figure 8.5-4 interval timer function settings (16-bit mode) in 16-bit mode, the timer 1 control register (t1cr) controls the timer. the timer 2 control register (t2cr) must, however, still be initialized. the data to be compared with the 16-bit counter is set in both data registers: the upper 8 bits in t2dr and the lower 8 bits in t1dr. all 16 bits of the counter are cleared simultaneously. all other operation in the 16-bit mode is the same as timer 1 operation in 8-bit mode. ff h e0 h 80 h 00 h counter count compare value (e0 h ) t1dr value (e0 h ) t1dr value modified (e0 h ff h ) *1 time t1if bit cleared by the program counter clear *2 activate match match match t1str bit (t1stp = 0) to pin *1 if a new value is written to the data register during counter operation, the new value is used from the next cycle. *2 at activation, and each time a match is detected, the counter is cleared and the data register setting is loaded into the comparison data latch. compare value (ff h ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t1cr t1if t1ie t1os1 t1os0 t1cs1 t1cs0 t1stp t1str other than "11" t2cr t2if t2ie t2os1 t2os0 t2cs1 t2cs0 t2stp t2str 0011 t1dr sets the interval time (lower8 bits). t2dr sets the interval time (upper8 bits). : used bit : unused bit 1 : set "1". 0 : set "0 ".
237 8.6 operation of counter function 8.6 operation of counter function this section describes the operations of the counter function of the 8/16-bit timer/ counter. n operation of counter function m 8-bit mode figure 8.6-1 "counter function settings (8-bit mode)" shows the settings required to operate the timer 1 as the counter function in the 8-bit mode. figure 8.6-1 counter function settings (8-bit mode) counter operation in the 8-bit mode is the same as interval timer operation of timer 1 in 8-bit mode, except that an external clock is used in lieu of the internal clock. m 16-bit mode figure 8.6-2 "counter function settings (16-bit mode)" shows the settings required to operate the counter function in the 16-bit mode. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ddr2 0 t1cr t1if t1ie t1os1 t1os0 t1cs1 t1cs0 t1stp t1str sets value to be compared with counter. t2cr t2if t2ie t2os1 t2os0 t2cs1 t2cs0 t2stp t2str : used bit : unused bit 1 : set "1" 0 : set "0" other than "11"
238 chapter 8 8/16-bit timer/counter figure 8.6-2 counter function settings (16-bit mode) counter operation in the 16-bit mode is the same as interval timer operation in 16-bit mode, except that an external clock is used in lieu of the internal clock. figure 8.6-3 "operation of counter function in 16-bit mode" shows the counter function operation in the 16-bit mode. figure 8.6-3 operation of counter function in 16-bit mode check: when the counter value during operation is read out in 16-bit mode, always read it twice, and verify that a proper value is got before using it. bit 7bit 6bit 5b it 4 bit 3 bit 2 bit 1 bit 0 ddr2 0 t1cr t1if t1ie t1os1 t1os0 t1cs1 t1cs0 t1stp t1str t2cr t2if t2ie t2os1 t2os0 t2cs1 t2cs0 t2stp t2str 0011 0 t1dr sets the interval time (lower 8 bits). t2dr sets the interval time (upper 8 bits). : used bit : unused bit 1 : set 1. 0 : set 0. 0001 h 0002 h 0003 h 1388 h 0000 h 0001 h 0000 h 88 h 13 h 34 h 12 h 34 h 12 h 88 h 13 h external clock counter clear t1str bit (t1stp = 0) counter value comparison data latch 1 (compared with lower 8 bits) comparison data latch 2 (compared with upper 8 bits) t1dr register* (lower 8 bits setting) t2dr register* (upper 8 bits setting) t1if register load load data set (to 1234 h ) cleared by the program. * the desired timing and desired settings can be used. at activation, and each time a match is detected, the data register settings are loaded into the comparison data latches, and the counter is cleared.
239 8.7 operation of the square wave output initial setting function 8.7 operation of the square wave output initial setting function the square wave output can be set to the desired initial value using the timer 1 control register (t1cr). n operation of square wave output initial setting function the square wave output can be set to the desired initial value by the program, but this can be done only when the timer operation is stopped (t1cr: t1str = 0). figure 8.7-1 "square wave output initial setting equivalent circuit" shows an equivalent circuit for the square wave output control circuit initial setting. to perform the initial setting, follow the procedure in table 8.7-1 "square wave output initial setting procedure (t1cr register)". the operation of the square wave output when this is done is as shown in figure 8.7-2 "square wave output initial setting operation". figure 8.7-1 square wave output initial setting equivalent circuit dq q > dq q > dq q > dq q > t1str t1os1 t1os0 output enable signal sets output pin "h" (to set pin of t.ff) sets output pin "l" (to rst pin of t.ff) level latch level latch write strobe signal table 8.7-1 square wave output initial setting procedure (t1cr register) step settings and operation (1) to set the square wave output pin (to) "l", set the square wave output control bits (t1cr: t1os1, t1os0) first to "01b", then to "11b". to set the to pin "h", set the bits to "10b" then "11b". note: until the bits are written to "11b", the circuit simply holds the latched value, and the to pin level remains in its current or previous state. (2) if the square wave output control bits (t1os1, t1os0) are written to "11b" and the timer operation stopped (t1str = 0), the to pin will output the level corresponding to the level latch value (initial value). this can also be accomplished by setting t1os1, t1os0, and t1str simultaneously. if the timer activation bit is set (t1str= 1), the counter will start. (3) the square wave output is inverted each time the counter value matches the data register settings.
240 chapter 8 8/16-bit timer/counter figure 8.7-2 square wave output initial setting operation (1) (2) (3) p22/to pin state port *1 timer *2 square wave output previous square setting value * 1: when the t1os1 and t1os0 bits of the t1cr register are both "00 b ", the p22/to pin is a general-purpose port pin (p22). * 2: if either t1os1 or t1os2 bit is "1", the p22/to pin is a square wave output pin (to). wave output value
241 8.8 operation of 8/16-bit timer/counter stop and restart 8.8 operation of 8/16-bit timer/counter stop and restart this section describes the operation of stop and restart operation functions of the 8/ 16-bit timer/counter. n timer stop and restart operation is described for timer 1 only. timer 2, however, operates the same way. timer 1 is stopped and restarted using the timer 1 control register stop and start bits (t1cr: t1stp and t1str). ? to start the counter after clearing it, with "0" in t1str bit set t1stp, t1str bit to "01 b ". on the t1str bit rising edge, the counter will be cleared and start counting. ? to temporarily stop the counter and then resume counting (without clearing the counter). first stop the counter by setting t1stp, t1str to "11 b ", then set t1stp, t1str to "01 b " to resume counting where you left off. table 8.8-1 "timer stop and restart" lists the timer states for each t1stp, t1str bit, and operation when the timer is activated from that state (t1stp, t1str = 01b). table 8.8-1 timer stop and restart t1stp (t2stp) t1str (t2str) timer state timer operation when counter is activated (t1stp, t1str="01b") from the state shown at the left 0 0 counter stopped counter cleared and starts counting 0 1 counter operating counter keeps on operating as-is 1 0 counter stopped counter cleared and starts counting 1 1 counter temporarily stopped counter resumes counting without being cleared
242 chapter 8 8/16-bit timer/counter 8.9 states in each mode during 8/16-bit timer/counter operation this section describes the operation of the 8/16-bit timer/counter when the device changes to sleep or stop mode or an operation halt request occurs during operation. n operation during subclock mode, standby mode, or operation halt figure 8.9-1 "counter operation during subclock mode, standby mode, or operation halt" shows the counter value state when the device changes to sleep or stop mode, or an operation halt request occurs, during operation of the interval timer function or counter function (for timer 1). the counter halts an maintains its current value when the device changes to stop mode. operation starts again from the stored counter value after wake-up from stop mode by an external interrupt. therefore, the first interval time or external clock count is not correct value. always initialize the 8/16-bit timer/counter after wake-up from stop mode. operation when entering or exiting timeclock mode (stbc: tmd = 1) is the same as when entering or exiting stop mode. timeclock mode is cleared by a timeclock interrupt or external interrupt. when the counter is stopped temporarily (t1stp = 1), it holds the count it had when it was stopped. when it is restarted (t1stp= 0), it resumes counting from the count at which it was stopped.
243 8.9 states in each mode during 8/16-bit timer/counter operation figure 8.9-1 counter operation during subclock mode, standby mode, or operation halt ation halt * 0000 h counter value data register setting time counter clear activate match match match match match match t1str bit cleared by the program. t1if bit (t1ie bit) to pin slp bit (stbc register) wake-up from sleep mode by irq5 sleep mode stp bit (stbc register) stop mode external interrupt t1stp bit temporary stop *: the to pin goes to the high-impedance state during stop mode if the pin state specification bit in the standby control register (stbc: spl) is "1" and the to pin is not set to with a pull-up resistor (optional). when the spl bit is "0", the pin maintains its value prior to changing to stop mode.
244 chapter 8 8/16-bit timer/counter 8.10 notes on using 8/16-bit timer/counter this section lists points to note when using the 8/16-bit timer/counter. n notes on using 8/16-bit timer/counter m notes when counter is stopped this information is described for timer 1, but the same information applies to timer 2. as shown in figure 8.10-1 "operation when timer stop bit is used", if the clock is "l" when t1stp temporarily stops the timer, the count will be incremented by 1. this may also occur if the input clock is "l" after a temporary stop, and the t1stp and t1str bits are both written to "00b" simultaneously. when using the t1stp bit to temporarily stop the counter, first read out the counter value; then write t1str bit to "0". figure 8.10-1 operation when timer stop bit is used m error activating of by program 8/16-bit timer/counter is not synchronized with the start of counting-up using the selected count clock. therefore, the time from activating the counter to match the register setting may be shorter than the theoretical time by a maximum of one cycle of the count clock. figure 8.10-2 "error on starting counter operation" shows the error that occurs on standing counter operation. 01 h 02 h 01 11 00 01 h 02 h 01 11 00 03 h 04 h when input clock is "h" when input clock is "l" clock input to the timer (ec, internal clock) counter value t1stp, t1str bits (t1cr register) temporary stop temporary stop stop stop
245 8.10 notes on using 8/16-bit timer/counter figure 8.10-2 error on starting counter operation m using one 8-bit channel when 8/16-bit timer/counter timer 1 only is used in the 8-bit mode, before doing so, first set the timer count clock select bits of the timer 2 control register (t2cr: t2cs1, t2cs0) to some state other than "11 b ". failure to do so may result in faulty operation. m notes on setting by program ? when the 8/16-bit timer/counter timer 1 only is used in the 16-bit mode, the timer 2 control register count clock select bits (t2cr: t2cs1, t2cs0) should always be set to "11 b " and bits 5 and 4, the unused bits (t2cr: tsos1, tsos0) to "00 b ". ? in 16-bit mode, when the counter value is read out during operation, always read it twice and verify that a proper value is got before using it. ? while the timer is operating (t1cr: t1str = 1), performing the initial state setting will not immediately cause the square wave output level to change. the output state will be initialized when the timer stops. ? interrupt processing cannot return if the interrupt request flag bit (t1cr: t1if, t2cr: t2if) is "1" and the interrupt request enable bit is enabled (t1cr: t1ie= "1", t2cr: t2ie= "1"). always clear the interrupt request flag bit. ? the interrupt request flag bit (tlcr: t1if or t2cr: t2if) is not set if the counter is disabled by the timer start bit (t1cr: t1str=0 or t2cr: t2cr =0) at the same time as an interrupt source is generated. 01234 count clock one cycle error cycle for 0 count counter activates counter count
246 chapter 8 8/16-bit timer/counter 8.11 program examples for 8/16-bit timer/counter this section gives a program examples for 8/16-bit timer/counter. n program example for interval timer function m processing description ? using timer 1 only, in 8-bit mode, generates repeated interval timer interrupts at 20 ms intervals. ? outputs a square wave to the to pin that inverts after each interval time. ? with a main clock master oscillation f ch of 4.2 mhz, and the highest speed main clock selected by the speed-shift function (1 instruction cycle time = 4/f ch ), and with an internal clock period of 512 t inst selected as the count clock, the t1dr setting for an interval of approximately 20 ms is calculated as follows: t1dr register value = 20 ms/(512 4/4.2 mhz) - 1 = 40.0 (28 h ) m coding example t2cr t1cr t2dr t1dr t1if ilr2 int_v irq5 equ equ equ equ equ equ dseg org dw ends 0018h 0019h 001ah 001bh t1cr:7 007dh abs 0fff0h wari ; address of the timer 2 control register ; address of the timer 1 control register ; address of the timer 2 data register ; address of the timer 1 data register ; define the timer 1 interrupt request flag bit. ; address of the interrupt level setting register 2 ; set interrupt vector. ;---------- main program ---------------------------------------------------------------------------------------------- cseg ; [code segment] ; stack pointer (sp) etc. are already initialized.
247 8.11 program examples for 8/16-bit timer/counter n program example for pulse counter function m processing description ? using timer 1 and timer 2 in 16-bit mode, count external clocks input to the ec pin, and generate an interrupt once for each 5000 clocks (1388 h ). ? shows a sample program (read16) for reading out the count in the 16-bit counter, while the counter is counting. : clri mov mov mov mov mov mov seti ilr2,#11111011b t2cr,#00000010b t1cr,#00011000b t1dr,#28h t1cr,#00111000b t1cr,#11111001b ; disable interrupts. ; set interrupt priority to level 2. ; clear timer 2 interrupt request flag, disable interrupt request ; output, set other than 16-bit mode, stop operation. ; clear timer 1 interrupt request flag, initialize square wave ; output "l", select 512 tinst, and stop operation. ; set value compared with the counter value (interval time). ; output "l" at square wave output pin (to). ; timer 1 interrupt request, clear counter, and start timer ; enable cpu interrupts. : ;---------- interrupt program --------------------------------------------------------------------------- wari clrb push w xchw push w : t1if a a, t a ; clear interrupt request flag. user processing : popw xchw popw reti ends a a, t a ;-------------------------------------------------------------------------------------------------------------- end
248 chapter 8 8/16-bit timer/counter m coding example ddr2 t2cr t1cr t2dr t1dr t1if ilr2 nt_v irq5 equ equ equ equ equ equ equ dseg org dw ends 000dh 0018h 0019h 001ah 001bh t1cr:7 007dh abs 0fff0h wari ; address of the port 2 data direction register ; address of the timer 2 control register ; address of the timer 1 control register ; address of the timer 2 data register ; address of the timer 1 data register ; define the timer 1 interrupt request flag bit. ; address of the interrupt level setting register 2 ; set interrupt vector. ;---------- main program -------------------------------------------------------------------------------------------- cseg ; [code segment] ; stack pointer (sp) etc. are already initialized. : mov clri mov mov mov mov mov seti ddr2,#00000000b ilr2,#11111011b t1dr,#088h t2dr,#013h t2cr,#00001100b t1cr,#01001101b ; set p20/ec pin as an input. ; disable interrupts. ; set interrupt level 2. ; set lower 8 bits of counter comparison value. ; set upper 8 bits of counter comparison value. ; set timer 2 to 16-bit mode. ; clear timer 1 interrupt request flag, enable interrupt ; request output, set p22/to ; as general-purpose port (p22), select external clock, ; clear counter, and start operation. ; enable cpu interrupts. : ;---------- data read subroutine ---------------------------------------------------------------------- : read16 movw movw cmpw beq xchw cmpw bne ret a,t2dr a,t2dr a ret16 a,t a a read16 ; 16-bit read, t1dr + t2dr. ; 16-bit read, t1dr + t2dr, save old value in t register. ; check first and second reads, compare a and t registers. ; if match, return. ; old value + 1 ; if mismatch, read again. : ;---------- interrupt program ---------------------------------------------------------------------
249 8.11 program examples for 8/16-bit timer/counter wari clrb pushw xchw pushw t1if a a,t a ; clear interrupt request flag. : user process : popw xchw popw reti ends a a,t a ;----------------------------------------------------------------------------------------------------------- end
250 chapter 8 8/16-bit timer/counter
251 chapter 9 external interrupt circuit 1 (edge) this chapter describes the functions and operation of the external interrupt circuit 1 (edge). 9.1 "overview of external interrupt circuit 1" 9.2 "block diagram of external interrupt circuit 1" 9.3 "structure of external interrupt circuit 1" 9.4 "external interrupt circuit 1 interrupts" 9.5 "operation of external interrupt circuit 1" 9.6 "program example for external interrupt circuit 1"
252 chapter 9 external interrupt circuit 1 (edge) 9.1 overview of external interrupt circuit 1 the external interrupt circuit 1 detects edges on the signals input to the four external interrupt pins and generates the corresponding interrupt requests to the cpu. n external interrupt circuit 1 function (edge detection) the external interrupt circuit 1 function detects specified edges on signals input to the external interrupt pins and to generate interrupt requests to the cpu. these interrupts can wake up the cpu from standby mode and change the device to the normal operating state (main-run or sub- run mode). external interrupt pins : 4 pins (p10/int10 to p13/int13) external interrupt source : inputs a specified edge (rising edge or falling edge) on the signal input to an external interrupt pin. interrupt control : enable or disable to input external interrupts and to output in interrupt requests, by the external interrupt 1 control register (eie1). interrupt flags : detects specified edges by the external interrupt request flag bits in the external interrupt 1 flag register (eif1). interrupt requests : separate interrupt requests are generated for each external interrupt source (irq0, irq1, irq2, and irq3).
253 9.2 block diagram of external interrupt circuit 1 9.2 block diagram of external interrupt circuit 1 the external interrupt circuit 1 consists of the following three blocks: ? edge detector ? external interrupt 1 control register (eie1) ? external interrupt 1 flag register (eif1) n block diagram of external interrupt circuit 1 figure 9.2-1 block diagram of external interrupt circuit 1 m edge detector circuit the signals received at the external interrupt pins (int10 to int13) are either inverted or not inverted, based on the state of the corresponding signal inversion (siv) bit of the eie1 register. if external interrupt inputs are enabled, a falling edge is detected in one of the inverted or non- inverted signals, and the interrupt request flag bit for that int pin (if10 to if13) is set to "1". m eie1 register the states of the signal inversion bits (siv0 to siv3) of this register determine whether the corresponding external interrupt input signal will be inverted. the external interrupt enable bits (ie10 to ie13) simultaneously enable or disable both the interrupt inputs and the interrupt request outputs. pin if13 if12 if11 if10 pin pin pin exor exor exor exor s q r2x r1x s q r2x r1x s q r2x r1x s q r2x r1x siv3 siv2 siv1 siv0 ie13 ie12 ie11 ie10 irq3 irq2 irq1 irq0 p13/int13 p12/int12 p11/int11 p10/int10 inversion control edge detector interrupt request output enable interrupt input enable interrupt request clear eie1 eif1 4 4 4 4 4
254 chapter 9 external interrupt circuit 1 (edge) m eif1 register the external interrupt request flag bits (if10 to if13) of this register are used to check interrupt request status and clear the interrupt requests.
255 9.3 structure of external interrupt circuit 1 9.3 structure of external interrupt circuit 1 this section describes the pins, pin block diagram, registers, and interrupt sources of the external interrupt circuit 1. n external interrupt circuit 1 pins the external interrupt circuit 1 uses four external interrupt pins. the external interrupt pins can function either as external interrupt inputs (hysteresis inputs) or as general-purpose i/o ports. when p10/int10 to p13/int13 pins are set as inputs in their port 1 data direction register (ddr1), and the corresponding external interrupt inputs are enabled in the external interrupt 1 control register (eie1) they operate as external interrupt input pins (int10 to int13). when they are being used as the port, the pin states, can be read from the port data register (pdr1) at any time table 9.3-1 "external interrupt circuit 1 pins" lists the pins associated with external interrupt circuit 1. table 9.3-1 external interrupt circuit 1 pins external interrupt pin when used as external interrupt input (interrupt input enabled) when used as general-purpose i/o port (interrupt input disabled) p10/int10 int10(eie1:ie10=1,ddr1:bit0=0) p10 (eie1:ie10=0) p11/int11 int11(eie1:ie11=1,ddr1:bit1=0) p11 (eie1:ie11=0) p12/int12 int12(eie1:ie12=1,ddr1:bit2=0) p12 (eie1:ie12=0) p13/int13 int13(eie1:ie13=1,ddr1:bit3=0) p13 (eie1:ie13=0)
256 chapter 9 external interrupt circuit 1 (edge) n block diagram of external interrupt circuit 1 pins figure 9.3-1 block diagram of external interrupt circuit 1 pins for mb89983 figure 9.3-2 block diagram of external interrupt circuit 1 pins for mb89p985 and mb89pv980 note: pins with a pull-up register (optional) go to the "h" level during a reset or in stop and watch mode (spl = "1"). pdr (port data register) ddr internal data bus pdr read pdr read (for bit manipulation instructions) output latch pdr write ddr write (port data direction register) pin spl: pin state specification bit in the standby control register (stbc) n-ch p-ch stop, watch mode (spl = 1) to external interrupt circuit external interrupt input enable stop, watch mode pull-up resistor (approx. 50 k /5.0 v) r p-ch p10/int10 p11/int11 p12/int12 p13/int13 pdr (port data register) ddr internal data bus pdr read pdr read ( for bit manipulation instructions) output latch pdr write ddr write (port data direction register) pin spl: pin state specification bit in the standby control register (stbc) n-ch p-ch p-ch stop, watch mode (spl = 1) to external interrupt circuit external interrupt input enable stop, watch mode p ull up control register pull-up resistor (approx. 50 k /5.0 v) p10/int10 p11/int11 p12/int12 p13/int13
257 9.3 structure of external interrupt circuit 1 n external interrupt circuit 1 registers figure 9.3-3 external interrupt circuit 1 registers n external interrupt circuit 1 interrupt sources eie1 (external interrupt 1 control register) eif1 (external interrupt 1 flag register) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0030 h siv3 siv2 siv1 siv0 ie13 ie12 ie11 ie10 00000000 b r/w r/w r/w r/w r/w r/w r/w r/w address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0031 h if13 if12 if11 if10 ----0000 b r/w r/w r/w r/w r/w: readable and writable : unused x: indeterminate irq0: external interrupt circuit generates an interrupt request (irq0) if an edge of the selected polarity is input to the external interrupt pin (int0) when external interrupt is enabled (eic1: eie0 = "1"). irq1: external interrupt circuit generates an interrupt request (irq1) if an edge of the selected polarity is input to the external interrupt pin (int1) when external interrupt is enabled (eic1: eie1 = "1"). irq2: external interrupt circuit generates an interrupt request (irq2) if an edge of the selected polarity is input to the external interrupt pin (int2) when external interrupt is enabled (eic2: eie2 = "1"). irq3: external interrupt circuit generates an interrupt request (irq3) if an edge of the selected polarity is input to the external interrupt pin (int3) when external interrupt is enabled (eic2: eie3 = "1").
258 chapter 9 external interrupt circuit 1 (edge) 9.3.1 external interrupt 1 control register (eie1) the external interrupt 1 control register (eie1) is used to select the inversion or non- inversion of interrupt input signal and to select enable or disable interrupts for external interrupt pins (int10 to int13). n external interrupt 1 control register (eie1) figure 9.3-4 external interrupt 1 control register (eie1) note: for mb89p985 and mb89pv980, there will be current leakage through the pull-up resistor in stop mode when the pull-up resistor is enabled and any enabled external interrupt 1 pin is input "0". to prevent the current leakage, the pull-up resistor should be disabled for each address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0030h siv3 siv2 siv1 siv0 ie13 ie12 ie11 ie10 00000000 b r/w r/w r/w r/w r/w r/w r/w r/w ie10 to ie13 external interrupt enable bits 0 disables external interrupt input and interrupt request output 1 enables external interrupt input and interrupt request output siv0 to siv3 external interrupt input si gnal inversion bits 0 external interrupt input signal not inverted (detect falling edge at pin). 1 external int errupt input signal inverted (detect rising edge at pin). r/w : readable and writable x : indeterminate : initial value table 9.3-2 external interrupt 1 control register (eie1) bits vs. interrupts pins bit external interrupt pin interrupt bit 7 bit 3 siv3 ie13 int13 irq3 bit 6 bit 2 siv2 ie12 int12 irq2 bit 5 bit 1 siv1 ie11 int11 irq1 bit 4 bit 0 siv0 ie10 int10 irq0
259 9.3 structure of external interrupt circuit 1 enabled interrupt pin before going into stop mode. table 9.3-3 external interrupt 1 control register (eie1) bits bit function bit 7 bit 6 bit 5 bit 4 siv3 to siv0: external interrupt input signal inversion bits ? select inversion/non-inversion of signal input to external interrupt pin. ? a value of "0" has the effect of selecting falling edge detection for that pin, and a "1" selects rising edge detection. bit 3 bit 2 bit 1 bit 0 ie13 to ie10: external interrupt enable bits enables or disables both the external interrupt input, and the interrupt request output to the cpu. an interrupt request output when both this bit and the corresponding external interrupt request flag bit (if13 to if10) are "1". note: when using an external interrupt pin, set it as an input by writing its bit in the port 1 data direction register (ddr1) to "0". the state of the external interrupt pin can always be read directly out of the port 1 data register (pdr1) regardless of the state of this interrupt enable bit.
260 chapter 9 external interrupt circuit 1 (edge) 9.3.2 external interrupt 1 flag register (eif1) external interrupt 1 flag register (eif1) is used to hold the irq state when an interrupt edge has been detected, and to clear the interrupt. n external interrupt 1 flag register (eif1) figure 9.3-5 external interrupt 1 flag register (eif1) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0031h if13if12if11if10 ----0000b r/w r/w r/w r/w if10 to if13 external int errupt request flag bits read write 0 no external irq (specified edge not detected). clear this bit 1 have external irq (specified edge detected). no effect. the bit does not change r/w : readable and writable : unused x : indeterminate : initial value table 9.3-4 external interrupt 1 flag register (eif1) bits bit external interrupt pin interrupt bit 3 if13 int13 irq3 bit 2 if12 int12 irq2 bit 1 if11 int11 irq1 bit 0 if10 int10 irq0
261 9.3 structure of external interrupt circuit 1 table 9.3-5 external interrupt 1 control register (eie1) bits bit function bit 7 bit 6 bit 5 bit 4 unused bits ? this read value is indeterminate. ? writing to this bit has no effect on the operation. bit 3 bit 2 bit 1 bit 0 if13 to if10: external interrupt request flag bits ? when a rising or falling edge, as specified by the state of the external interrupt in put signal inversion bit (siv3 to siv0), the corresponding irq flag bit is set to "1". ? when both this bit and the corresponding interrupt enable bit (eie1: ie13 to ie10) are set to "1", that irq is sent to the cpu. ? writing "0" clears this bit. writing "1" has no effect and does not change the bit value. note: when the external interrupt enable bits (eie1: ie13 to ie10) are cleared to "0", the external interrupt inputs are disabled at the same time, which means that in this state, these bits will not be changed even when the specified edge is input.
262 chapter 9 external interrupt circuit 1 (edge) 9.4 external interrupt circuit 1 interrupts the external interrupt circuit 1 can generate interrupt requests when it detects a specified edge on the signal input to an external interrupt pin. n interrupts for external interrupt circuit 1 operation if external interrupts are enabled (eie1: ie10 to ie30 = 1) and the specified edge is detected at the external interrupt input, the corresponding external irq flag bit (eif1: if10 to if13) is set to "1" and the corresponding irq (irq0 to irq3) sent to the cpu. write "0" to the corresponding external interrupt request flag bit in the interrupt processing routine to clear the interrupt request. check: when enabling interrupts (eie1: ie10 to ie13 = "1") after wake-up from a reset, always clear the corresponding external interrupt request flag bit (eie1: if10 to if13 = "0") in advance. also, interrupt processing cannot return if the external interrupt request flag bit is "1" and the interrupt request enable bit is enabled. in the interrupt processing routine, always clear the external interrupt request flag bit. notes: changing a signal inversion bit from the "non-invert" to the "invert" state while the int pin is "h", or from "invert" to "non-invert" while the pin is low, will cause the external interrupt request flag bit (eif1: if10 to if13) to be set immediately. changing an external interrupt bit from "disable" to "enable" (eie1: ie10 to ie13: 0 --> 1) may also set the external irq flag bit. for this reason, you should make the inversion or enable bit changes with interrupts in the disabled state, then clear irq flags before enabling interrupts again. an interrupt request is generated immediately if the external interrupt request flag bit is "1" when the external interrupt enable bit is changed from disabled to enabled ("0" --> "1"). wake-up from stop mode by an interrupt is possible using only the external interrupt circuit 1 and 2. perform with interrupts disabled, then clear external irq flags before enabling interrupts.
263 9.4 external interrupt circuit 1 interrupts n register and vector table for external interrupt circuit 1 interrupts reference: see section 3.4.2 "interrupt processing" for details on the interrupt operation. table 9.4-1 register and vector table for external interrupt circuit 1 interrupts irq interrupt level setting register vector table address register setting bits upper lower irq0 ilr1 (007ch) l01 (bit1) l00 (bit0) fffa h fffb h irq1 l11 (bit3) l10 (bit2) fff8 h fff9 h irq2 l21 (bit5) l20 (bit4) fff6 h fff7 h irq3 l31 (bit7) l30 (bit6) fff4 h fff5 h
264 chapter 9 external interrupt circuit 1 (edge) 9.5 operation of external interrupt circuit 1 the external interrupt circuit 1 sends an interrupt request to the cpu when it detects a specified edge at one of its external interrupt pins. n operation of external interrupt circuit 1 figure 9.5-1 "external interrupt circuit 1 settings" settings shows the settings required to operate the external interrupt circuit 1. figure 9.5-1 external interrupt circuit 1 settings the input signals from the external interrupt pins (int10 to int13) are either inverted or not, depending on the state of the applicable external interrupt signal inversion bit (eie1: siv0 to siv3). if the external interrupt enable bit (eie1: ie10 to ie13) is "1", the corresponding external interrupt request flag bit (eif1: if10 to if13) will be set to "1" when a falling edge is detected in the inverted/non-inverted signal. figure 9.5-2 "operation of external interrupt 1 (int10)" shows the external interrupt 1 operation (for signals received at pin int10). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 eie1 siv3 siv2 siv1 siv0 ie13 ie12 ie11 ie10 eif1if13if12if11if10 ddr1 : used bit : unused bit : set bits for pins used for external interrupts to "0"
265 9.5 operation of external interrupt circuit 1 figure 9.5-2 operation of external interrupt 1 (int10) note: the pin state can be read directly from the port data register (pdr6), even when used as an external interrupt pins. if10 bit ie10 bit siv0 bit input waveform to the int10 pin if10 bit cleared at the same time as the ie10 bit is set. interrupt request flag bit cleared by the program. interrupt signal inverted (detect rising edge) interrupt signal not inverted (detect falling edge) irq0
266 chapter 9 external interrupt circuit 1 (edge) 9.6 program example for external interrupt circuit 1 this section gives a program example for the external interrupt circuit 1. n program example for external interrupt circuit 1 m processing description ? generates interrupts on detecting a falling edge input to the int10 pin. m coding example ddr eie1 eif1 equ equ equ 0003h 0030h 0031h ; address of the port 1 data direction register ; address of the external interrupt 1 control register ; address of the external interrupt 1 flag register ie10 siv0 if10 equ equ equ eie1:0 eie1:4 eie1:0 ; define the external interrupt enable bit. ; define the external interrupt signal inversion bit. ; define the external interrupt request flag bit. ilr1 equ 007ch ; address of the set interrupt level settings register int_v irq0 int_v dseg org dw ends abs 0fffah wari ; [data segment] ; set interrupt vector. ;---------- main program ---------------------------------------------------------------------------------------- cseg : clri mov mov clrb setb clrb seti : ilr1,#11111110b ddr0,#00000000b siv0 ie10 if10 ; [code segment] ; stack pointer (sp) etc. are already initialized. ; disable interrupts. ; set interrupt priority to level 2. ; set p10/int10 pin as input. ; select falling edge. ; enable int10 interrupt input. ; clear external interrupt request flag. ; enable interrupts. ;---------- interrupt processing routine ---------------------------------------------------------------------- wari clrb pushw xchw pushw : if10 a a,t a ; clear external interrupt request flag. user processing
267 9.6 program example for external interrupt circuit 1 : popw xchw popw reti ends a a,t a ;---------------------------------------------------------------------------------------------------------------------- end
268 chapter 9 external interrupt circuit 1 (edge)
269 chapter 10 external interrupt circuit 2 (level) this chapter describes the functions and operation of the external interrupt circuit 2 (level). 10.1 "overview of external interrupt circuit 2" 10.2 "block diagram of external interrupt circuit 2" 10.3 "structure of external interrupt circuit 2" 10.4 "external interrupt circuit 2 interrupt" 10.5 "operation of external interrupt circuit 2" 10.6 "program example for external interrupt circuit 2"
270 chapter 10 external interrupt circuit 2 (level) 10.1 overview of external interrupt circuit 2 the external interrupt circuit 2 detects the level of the signals input to the eight external interrupt pins and generates the interrupt requests to the cpu. n external interrupt circuit 2 function (level detection) the external interrupt circuit 2 function detects the signals of the "l" levels input to the external interrupt pins and to generate interrupt request to the cpu. these interrupts can wake up the cpu from standby mode and change the device to the normal operating state (main-run or sub- run mode). external interrupt pins: 8 pins (p00/int20 to p07/int27 ) external interrupt sources: "l" level signal input to an external interrupt pin. interrupt control: enables or disables to input external interrupt controlled by external interrupt 2 control register (eie2) interrupt flag: irq flag bit of external interrupt 2 flag register (eif2). flag set when there is an irq. interrupt request: irq4 is generated if any enabled external interrupt pin goes low.
271 10.2 block diagram of external interrupt circuit 2 10.2 block diagram of external interrupt circuit 2 the external interrupt circuit 2 consists of the following three blocks: ? interrupt request generator ? external interrupt 2 control register (eie2) ? external interrupt 2 flag register (eif2) n block diagram of external interrupt circuit 2 figure 10.2-1 block diagram of external interrupt circuit 2 m interrupt request generator the interrupt request generator generates cpu interrupt requests based on signals input at external interrupt pins (int20 to int27 ) and the external interrupt enable bits. m eie2 register external interrupt input enable bits (ie20 to ie27) enable/disable "l" level signals input at the corresponding external interrupt input pins. m eif2 register the interrupt request flag bit of this register (if20) is used to hold (and clear) interrupt request signals. p00/int20 p01/int21 p02/int22 p03/int23 p04/int24 p05/int25 p06/int26 p07/int27 eie2 eif2 ie27 ie26 ie25 ie24 ie23 ie22 ie21 ie20 if20 pin pin pin pin pin pin pin pin irq generator circuit external interrupt request irq4 interrupt generator request
272 chapter 10 external interrupt circuit 2 (level) 10.3 structure of external interrupt circuit 2 this section describes the pins, pin block diagram, registers, and interrupt sources of the external interrupt circuit 2. n external interrupt circuit 2 pins the external interrupt circuit 2 uses eight external interrupt pins. the external interrupt pins can function either as external interrupt inputs (hysteresis inputs) or as general-purpose i/o ports. when p00/int20 to p07/int27 pins are set as inputs in the port 0 data direction register (ddr0), and the corresponding external interrupt inputs are enabled in the external interrupt 2 control register (eie2) they operate as external interrupt input pins (int20 to int27 ). when they are being used as the input port, the pin states can be read from the port data register (pdr0) at any time. table 10.3-1 "external interrupt circuit 2 pins" lists the external interrupt circuit 2 pins. table 10.3-1 external interrupt circuit 2 pins external interrupt pin when used as external interrupt input (interrupt input enabled) when used as general-purpose i/o port (interrupt input disabled) p00/int20 int20 (eie2:ie20=1, ddr0:bit0=0) p00 (eie2:ie20=0) p01/int21 int21 (eie2:ie21=1, ddr1:bit1=0) p01 (eie2:ie21=0) p02/int22 int22 (eie2:ie22=1, ddr2:bit2=0) p02 (eie2:ie22=0) p03/int23 int23 (eie2:ie23=1, ddr3:bit3=0) p03 (eie2:ie23=0) p04/int24 int24 (eie2:ie24=1, ddr4:bit4=0) p04 (eie2:ie24=0) p05/int25 int25 (eie2:ie25=1, ddr5:bit5=0) p05 (eie2:ie25=0) p06/int26 int26 (eie2:ie26=1, ddr6:bit6=0) p06 (eie2:ie26=0) p07/int27 int27 (eie2:ie27=1, ddr7:bit7=0) p07 (eie2:ie27=0)
273 10.3 structure of external interrupt circuit 2 n block diagram of external interrupt circuit 2 pins figure 10.3-1 block diagram of external interrupt circuit 1 pins for mb89983 figure 10.3-2 block diagram of external interrupt circuit 2 pins for mb89p985 and mb89pv980 note: pins with a pull-up register (optional) go to the "h" level during a reset or in stop and watch mode (spl = "1"). pdr (port data register) ddr internal data bus pdr read pdr read (for bit manipulation instructions) output latch pdr write ddr write (port data direction register) pin spl: pin state specification bit in the standby control register (stbc) n-ch p-ch stop, watch mode (spl = 1) to external interrupt circuit external interrupt input enable stop, watch mode pull-up resistor (approx. 50 k /5.0 v) r p-ch p00/int20 to p07/int27 pdr (port data register) ddr internal data bus pdr read pdr read (for bit manipulation instructions) output latch pdr write ddr write (port data direction register) pin spl: pin state specification bit in the standby control register (stbc) n-ch p-ch p-ch stop, watch mode (spl = 1) to external interrupt circuit external interrupt input enable stop, watch mode pull up control register pull-up resistor (approx. 50 k /5.0 v) p00/int20 to p07/int27
274 chapter 10 external interrupt circuit 2 (level) n external interrupt circuit 2 registers figure 10.3-3 external interrupt circuit 2 registers n external interrupt circuit 2 interrupt sources eie2 (external interrup t 2 control register) eif2 (external interrup t 2 flag register) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0032 h ie27 ie26 ie25 ie24 ie23 ie22 ie21 ie20 00000000 b r/w r/w r/w r/w r/w r/w r/w r/w address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0033 h if20 -------0 b r/w r/w: readable and writable : unused x : indeterminate irq4: irq4 is generated if any one of external interrupt pins int20 to int27 goes to "l" with a "1" in the external interrupt input enable bit for that pin.
275 10.3 structure of external interrupt circuit 2 10.3.1 external interrupt 2 control register (eie2) the external interrupt 2 control register (eie2) is used to enable/disable input of external interrupt pins (int20 to int27 ). n external interrupt 2 control register (eie2) figure 10.3-4 external interrupt 2 control register (eie2) note: for mb89p985 and mb89pv980, there will be current leakage through the pull-up resistor in stop mode when the pull-up resistor is enabled and any enabled external interrupt 2 pin is input "0". to prevent the current leakage, the pull-up resistor should be disabled for each enabled interrupt pin before going into stop mode. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0032 h ie27 ie26 ie25 ie24 ie23 ie22 ie21 ie20 00000000 b r/w r/w r/w r/w r/w r/w r/w r/w ie20 to ie27 external interrupt input enable bits 0 disables external interrupt input 1 enables external interrupt input r/w : readable and writable : unused x : indeterminate : initial value table 10.3-2 external interrupt 2 control register (eie2) bits vs. pins bit pin bit 7 ie27 int27 bit 6 ie26 int26 bit 5 ie25 int25 bit 4 ie24 int24 bit 3 ie23 int23 bit 2 ie22 int22 bit 1 ie21 int21 bit 0 ie20 int20
276 chapter 10 external interrupt circuit 2 (level) table 10.3-3 external interrupt 1 control register (eie1) bits bit function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ie27 to ie20: external interrupt enable bits ? these bits enable/disable input of external interrupts at external interrupt pins int20 to int27 . ? setting these bits to "1" puts the corresponding pin into its external interrupt input mode, and enables input of external interrupts at the pin. ? conversely, a "0" in the bit allows the pin to function in its general-purpose port mode and inhibits input of interrupts at the pin. note: when using a pin for external interrupts, set it as an input by writing its bit in the port 0 data direction register (ddr0) to "0". the state of the pin can always be read directly out of the port 0 data register (pdr0) regardless of the sate of this external interrupt enable bit.
277 10.3 structure of external interrupt circuit 2 10.3.2 external interrupt 2 flag register (eif2) external interrupt 2 flag register (eif2) is used to hold the irq state when a level interrupt has been detected, and clear the interrupt. n external interrupt 2 flag register (eif2) figure 10.3-5 external interrupt 2 flag register (eif2) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0033 h if20 -------0 b r/w ie20 external interrupt request flag bit read write 0 no external irq (l level not detected). clears this bit. 1 have external irq (l level detected). no effect. this bit does not change r/w : readable and writable : unused x : indetermina te : initial value table 10.3-4 external interrupt 1 control register (eie1) bits bit function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 unused bits ? the read value is indeterminate. ? writing to this bit has no effect on the option. bit 0 if20: external interrupt request flag bit ? this bit is set to "1" when a "l" is detected at an enabled external input pin (int20 to int27 ). ? writing "0" clears this bit. writing "1" has no effect and does not change the bit value. note: writing "0" to the external interrupt enable bits of the external interrupt 2 control register (eie2: ie20 to ie27) simply disables the corresponding external interrupt input; it does not clear the interrupt request. irq4 will continue to be sent to the cpu until it is cleared by writing "0" to the if20 bit.
278 chapter 10 external interrupt circuit 2 (level) 10.4 external interrupt circuit 2 interrupt the external interrupt circuit 2 interrupt trigger event is the detection of a "l" level at the external interrupt pin. n interrupts for external interrupt circuit 2 operation if a "l" is detected at an enabled external interrupt pin, the external interrupt request flag bit (eif2: if20) is set to "1", and an interrupt request (irq4) to the cpu is generated. write "0" to the if20 bit in the interrupt processing routine to clear the interrupt request. once the external interrupt request flag bit (if20) is set to "1", irq4 continues to be asserted as long as the flag set. disabling the interrupt input by writing the ie bit (ie20 to ie27) of the eie2 register to "0" will not clear the interrupt request. always clear the if20 bit. also, if the external interrupt pin stays "l", writing "0" to the if20 bit without disabling the external interrupt input will not clear the interrupt either, because if20 will immediately be set again by the "l" pin. after an interrupt request is generated, then, either the input must be disabled, or the external irq signal de-asserted. check: when enabling interrupts of cpu after wake-up from a reset, clear the if20 bit in advance. note: wake-up from stop mode by an interrupt is possible using only the external interrupt circuit 1 and 2. n register and vector table for external interrupt circuit 2 interrupts reference: see section 3.4.2 "interrupt processing" for details on the interrupts operation. table 10.4-1 registers and vector table for external interrupt circuit 2 interrupts interrupt interrupt level setting register vector table address register setting bits upper lower irq4 ilr2 (007d h ) l41 (bit 1) l40 (bit 0) fff2 h fff3 h
279 10.5 operation of external interrupt circuit 2 10.5 operation of external interrupt circuit 2 the external interrupt circuit 2 sends an interrupt request to the cpu when it detects a "l" at one of its external interrupt pins. n operation of external interrupt circuit 2 figure 10.5-1 "external interrupt circuit 2 settings" shows the settings required to operate the external interrupt circuit 2. figure 10.5-1 external interrupt circuit 2 settings if a "l" is applied to one of the int20 to int27 pins with the corresponding external interrupt input enable bit (ie20 to ie27) in the "enable" state, the circuit sends an irq4 interrupt request to the cpu. figure 10.5-2 "operation of external interrupt 2 (int20)" shows external interrupt circuit 2 operation (for a signal received at int20). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 eie2 ie27 ie26 ie25 ie24 ie23 ie22 ie21 ie20 eif2if20 ddr0 ******** : used bit : set bits for pins used for external interrupts to 0
280 chapter 10 external interrupt circuit 2 (level) figure 10.5-2 operation of external interrupt 2 (int20 ) note: the pin state can be read directly from the port data register (pdr0) even when the pin is being used as an external interrupt input. reti eie2: ie20 pdr0: bit0 input waveform to the int20 pin ("l" level detected) external interrupt input enabled eif2: if20 (same as irq4) cleared by the interrupt processing routine. irq4 interrupt processing routine operation. interrupt processing interrupt processing can be read at any time. reti
281 10.6 program example for external interrupt circuit 2 10.6 program example for external interrupt circuit 2 this section gives a program example for the external interrupt circuit 2. n program example for external interrupt circuit 2 m processing description ? generates interrupts on detecting a "l" input the int20 pin. m coding example ddr0 eie2 eif2 equ equ equ 0001h 0032h 0033h ; address of port 0 data direction register ; address of external interrupt 2 control register ; address of external interrupt 2 flag register if20 equ eif2:0 ; define the external interrupt request flag bit. ilr2 equ 007dh ; address of the set interrupt level setting register 2 int_v irq4 int_v dseg org dw ends abs 0fff2h wari ; [data segment] ; set interrupt vector. ;---------- main program ------------------------------------------------------- cseg : clri clrb mov mov mov seti : if20 ilr2,#11111110b ddr0,#00000000b eie2,#00000001b ; [code segment] ; stack pointer (sp) etc. are already initialized. ; ; disable interrupts. ; clear external interrupt request flag. ; set interrupt priority (level 2). ; set p00/int20 pin as input. ; enable external interrupt input at int20 pin ; enable interrupts. ;---------- interrupt processing routine ----------------------------------------------------- wari mov clrb pushw xchw pushw eie2,#00000000b if20 a a,t ; disable external interrupt input at int20 pin. ; clear external interrupt request flag. : user processing :
282 chapter 10 external interrupt circuit 2 (level) popw xchw popw reti ends a a,t a ;--------------------------------------------------------------------------------------------------------------------------- end
283 chapter 11 a/d converter this chapter describes the functions and operation of the a/d converter. 11.1 "overview of a/d converter" 11.2 "block diagram of a/d converter" 11.3 "structure of a/d converter" 11.4 "a/d converter interrupts" 11.5 "operation of a/d converter" 11.6 "notes on using a/d converter" 11.7 "program example for a/d converter"
284 chapter 11 a/d converter 11.1 overview of a/d converter the a/d converter can be selected to function either as an 8-bit successive approximation type a/d conversion or as a sense function. the sense function performs a high-speed comparison between the input voltage and a set voltage. both functions select one input signal from the eight analog input pin channels and can be activated either by software, by an internal clock, or by an 8/16-bit timer output. n a/d conversion function the a/d conversion function converts the analog voltage (input voltage) input to an analog input pin to an 8-bit digital value. ? selects one input from eight analog input pins. ? conversion speed is 44 instruction cycles (41.9 m s with highest main clock and 4.2 mhz source oscillation). ? generates an interrupt when a/d conversion completes. ? conversion completion can also be determined by software. the following methods are available to activate a/d conversion: ? activation by software ? continuous activation by a timebase timer output (divide-by-2 8 main clock source oscillation) ? continuous activation by an 8/16-bit timer/counter output. n sense function the sense function compares the analog voltage (input voltage) input to an analog input pin with the voltage (compare voltage) corresponding to the value set in the a/d data register (adcd), and determines which voltage is higher or lower. ? selects one input from eight analog input pins. ? compare speed is 12 instruction cycles (11.4 s in main clock mode, with the highest clock speed selected, and a clock oscillator frequency of 4.2 mhz). ? generates an interrupt when the comparison condition is satisfied. the following methods are available to activate the sense function: ? activation by software ? continuous activation by a timebase timer output (divide-by-2 8 main clock source oscillation) ? continuous activation by an 8/16-bit timer/counter output.
285 11.2 block diagram of a/d converter 11.2 block diagram of a/d converter the a/d converter consists of the following nine blocks: ? clock selector (input clock selector for a/d converter activation) ? analog channel selector ? sample hold circuit ? d/a converter ? comparator ? controller ? a/d data register (adcd) ? a/d control register 1 (adc1) ? a/d control register 2 (adc2) n block diagram of a/d converter figure 11.2-1 block diagram of a/d converter adck adie admd ext adc2 internal data bus ans3 ans2 ans1 ans0 adi admv sifm ad adc1 2 8 /f ch t01 p53/an3 p52/an2 p51/an1 p50/an0 avr av cc av ss clock selector analog channel selector sample hold circuit comparator controller adcd register d/a converter f ch : main clock source oscillation irqb resv1 (timebase timer output) t01: 8/16-bit time r/counter 16-bit timer output (timer 1 output)
286 chapter 11 a/d converter m clock selector selects the clock used to activate the a/d conversion or sense function when continuous activation is enabled (adc2: ext = "1"). m analog channel selector selects one of the eight analog input channels. m sample hold circuit holds the input voltage selected by the analog channel selector. the circuit samples and holds the input voltage immediately after the a/d conversion or sense function is activated. this allows a/d conversion (or comparison) to proceed without being affected by input voltage fluctuation. m d/a converter generates the voltage corresponding to the value set in the adcd register. m comparator compares the sampled and held input voltage with the output voltage of the d/a converter, and determines which voltage is higher or lower. m controller the controller has two functions: ? for the a/d conversion function, the controller successively determines the value of each bit of the adcd register, starting from the most significant bit and proceeding to the least significant bit, based on the greater-than/less-than signal from the comparator. when conversion is complete, the circuit sets the interrupt request flag bit (adc1: adi). ? for the sense function, the controller sets the interrupt request flag bit (adi) if the greater- than/less-than signal from the comparator matches the compare condition setting bit (sifm) in the adc1 register. m adcd register the adcd register has two functions: ? stores the a/d conversion result for the a/d conversion function. ? for the sense function, the data for the voltage that is compared with the input voltage is written to this register. m adc1 register the adc1 register is used to enable or disable each function, select the analog input pin, check statuses, and control interrupts. m adc2 register the adc2 register is used to select the input clock, enable or disable interrupts, and select functions.
287 11.2 block diagram of a/d converter n a/d converter power supply voltage m av cc the a/d converter power supply pin. use at the same voltage as v cc . when high a/d conversion resolution is required, take measures to ensure that the noise on v cc is not present on av cc , or use a separate power supply. connect this pin to the power supply, even if the a/d converter is not used. m av ss the a/d converter ground pin. use at the same voltage as v ss . when high a/d conversion accuracy is required, take measures to ensure that the noise on v ss is not present on av ss . connect this pin to ground (gnd), even if the a/d converter is not used. m av r reference voltage input pin for the a/d converter. the a/d converter performs 8-bit a/d conversion between avr and av ss . connect to av ss if the a/d converter is not used.
288 chapter 11 a/d converter 11.3 structure of a/d converter this section describes the pins, pin block diagrams, registers, and an interrupt source for the a/d converter. n a/d converter pins the a/d converter function uses the p50/an0 to p53/an3 pins. these pins can function as either output-only ports of the n-ch open-drain outputs (p50 to p53), as the analog input pins (an0 to an3). an0 to an3: the analog voltages to be converted (a/d conversion function) or compared (sense function) are applied to these pins. to select the analog input function for one of these pins, you set the corresponding bit of the port data register (pdr5) to "1", to turn off the port output transistor, then set the analog input channel select bits (adc1: ans0 to ans3) to select the pin as the analog input channel. pins that are not needed for analog inputs can still be used as output port pins, even while the a/d converter is being used. n block diagram of a/d converter pin figure 11.3-1 block diagram of p53/an3 to p50/an0 pins for mb89983 pdr (port data register) internal data bus pdr read output latch pdr write pin spl: pin state specification bit in the standby control register (stbc) n-ch stop, watch mode (spl = 1) p-ch a/d converter channel selector a/d converter analog input p-ch pull-up resistor (approx. 50 k /5.0 v) p50/an0 p51/an1 p52/an2 p53/an3
289 11.3 structure of a/d converter figure 11.3-2 block diagram of p53/an3 to p50/an0 pins for mb89p985 and mb89pv980 check: if using the a/d converter, do not set a pull-up resistor for any of p53/an3 to p50/an0. check: do not use the pins as output ports if using as an analog input. n a/d converter registers figure 11.3-3 a/d converter registers pdr (port data register) internal data bus pdr read output latch pdr write pin spl: pin state specification bit in the standby control register (stbc) n-ch stop, watch mode (spl = 1) p-ch a/d converter channel selector a/d converter analog input p-ch pull up control register pull-up resistor (approx. 50 k /5.0 v) p50/an0 p51/an1 p52/an2 p53/an3 adc1 (a/d control register 1) adc2 (a/d control register 2) a dcd (a/d data register) r/w : readable and writable r : read-only : unused x : indeterminate address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 002d h ans3 ans2 ans1 ans0 adi admv sifm ad 00000000 b r/w r/w r/w r/w r/w r r/w r/w address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 002e h adck adie admd ext resv1 ---00001 b r/w r/w r/w r/w r/w address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value h xxxxxxxx b r/w r/w r/w r/w r/w r/w r/w r/w 002f
290 chapter 11 a/d converter n a/d converter interrupt source irqb: the a/d converter generates an interrupt request if an interrupt request output is enabled (adc2: adie = "1") when a/d conversion completes or the sense function detects the specified condition.
291 11.3 structure of a/d converter 11.3.1 a/d control register 1 (adc1) a/d control register 1 (adc1) is used to enable or disable the functions, select the analog input pin, and check the state of the a/d converter. n a/d control register 1 (adc1) figure 11.3-4 a/d control register 1 (adc1) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 002d h ans3 ans2 ans1 ans0 adi admv sifm ad 00000000 b r/w r/w r/w r/w r/w r r/w r/w ad a/d converter activation bit only applies when software activation is specified (adc2: ext = "0"). 0 does not activate the a/d conversion or sense function. 1 activates the a/d conversion or sense function. sifm compare condition setting bit only applies when the sense function is selected (adc2: admd = "1") 0 sets the interrupt request flag bit when the input voltage is less than the compare voltage. 1 sets the interrupt request flag bit when the input voltage is greater than the compare voltage. admv conversion-in-progress flag bit 0 conversion or comparison not currently in progress. 1 conversion or comparison in progress. adi interrupt request flag bit read write for the a/d conversion function for the sense function 0 conversion not complete. specified condition has not occurred. clears this bit. 1 conversion completes. specified condition occurred. no effect. the bit does not change. ans3 ans2 ans1 ans0 analog input channel selection bits 0 0 0 0 an0 pin 0001 an1 pin 0010 an2 pin 0011 an3 pin 0100 not available 0101 0110 0111 1 r/w : readable and writable r : read-only : initial value
292 chapter 11 a/d converter table 11.3-1 a/d control register 1 (adc1) bitss bit function bit 7 bit 6 bit 5 bit 4 ans3 to ans0: analog input channel selection bits these bits select which of the an0 to an3 pins to use as the analog input pin. when using software activation (adc2: ext = "0"), these bits can be modified to at the same time as activating the a/d conversion or sense function (ad = "1"). check: always set ans3 to "0". if ans3 is "1", no pin is selected as the analog input pin. also, disable general-purpose port output corresponding to the analog input pin. do not modify these bits when the admv bit is set to "1". note: pins not used as analog inputs can be used as general- purpose ports. bit 3 adi: interrupt request flag bit ? for the a/d conversion function: this bit is set to "1" when the a/d conversion is completed. ? for the sense function: this bit is set to "1" when the input voltage satisfies the condition set in the compare condition setting bit (sifm). ? an interrupt request is output for either function when both this bit and the interrupt request enable bit (adc2: adie) are "1". ? writing "0" clears this bit. writing "1" has no effect and does not change the bit value. bit 2 admv: conversion-in- progress flag bit this bit indicates whether or not the a/d conversion function is currently performing a conversion or the sense function is currently performing a voltage comparison. the bit is set to "1" when a conversion or comparison is in progress. note: this bit is read-only. the write value has no meaning and has no effect on the operation. bit 1 sifm: compare condition setting bit ? this bit has no meaning for the a/d conversion function. ? for the sense function: this bit sets the comparison condition for the input voltage and compare voltage that generates an interrupt source. an interrupt request is generated (adi = "1") when the input voltage is less than the compare voltage if the bit is "0", and when the input voltage is greater than the compare voltage if the bit is "1". no interrupt request is generated if the input voltage and compare voltage are equal. ? when using software activation (adc2: ext = "0"), this bit can be modified to at the same time as starting the sense function (ad = "1"). check: do not modify these bits when the admv bit is set to "1".
293 11.3 structure of a/d converter bit 0 ie13 to ie10: external interrupt enable bits ? this bit activates the a/d conversion or sense function by software. ? writing "1" to this bit activates the a/d conversion or sense function when continuous activation is not specified (adc2: ext = "0"). check: writing "0" to this bit does not stop the a/d conversion or sense function. the read value is always "0". this bit has no meaning when continuous activation is specified. table 11.3-1 a/d control register 1 (adc1) bitss bit function
294 chapter 11 a/d converter 11.3.2 a/d control register 2 (adc2) a/d control register 2 (adc2) is used to select the a/d converter functions, select the input clock, enable or disable interrupts and continuous activation, and check the state of the a/d converter. n a/d control register 2 (adc2) figure 11.3-5 a/d control register 2 (adc2) address bit 7 bit 6 bit5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 002e h adck adie admd ext resv ---00001 b r/w r/w r/w r/w r/w resv1 reserved bit always write "1" to this bit. ext continuous activation enable bit 0 activates by the ad bit in the adc1 register. 1 activates continuously by the clock selected in the adck bit. admd function selection bit 0 a/d conversion function 1 sense function adie interrupt request enable bit 0 disables interrupt request output. 1 enables interrupt request output. adck input clock selection bit only applies when continuous activation is ena bled (ext = "1"). 0 timebase timer output (divide-by-2 8 source oscillation) 1 8/16-bit timer 16-bit time output r/w : readable and wrtiable : unused x : indeterminate : initial value
295 11.3 structure of a/d converter table 11.3-2 a/d control register 1 (adc1) bitss bit function bit 7 bit 6 bit 5 unused bits ? the read value is indeterminate. ? writing to these bits has no effect on the operation. bit 4 adck: input clock selection bit ? this bit selects the input clock used to activate the a/d conversion or sense function when continuous activation is specified (ext = "1"). setting this bit to "0" selects the timebase timer output (divide=by=2 8 main clock source oscillation). setting this bit to "1" selects the 16-bit timer output (to1) in 8/16 timer/counter. check: in the subclock mode, the main clock oscillator is stopped, which means that the timebase timer output cannot be used to trigger continuous mode conversions/comparisons. bit 3 adie: interrupt request enable bit ? this bit enables or disables an interrupt request output to the cpu. ? an interrupt request is output when both this bit and the interrupt request flag bit (adc1: adi) are "1". bit 2 admd: function selection bit ? this bit switches between the a/d conversion function and sense function. ? the a/d converter operates as the a/d conversion function when this bit is set to "0" and as the sense function when this bit is set to "1". check: do not modify this bit when the conversion-in-progress bit (adc1: admv) is set to "1". also, clear the interrupt request flag bit (adc1: adi = "0") at switching functions. bit 1 ext: continuous activation enable bit ? this bit selects whether to activate the a/d conversion and sense functions by software or to operate continuously synchronized with an input clock. ? setting this bit to "0" enables software activation by the a/d converter activation bit (adc1: ad). setting this bit to "1" enables continuous activation on the rising edge of the clock selected in the input clock selection bit (adc2: adck). bit 0 resv1: reserved bit check: always write "1" to this bit. the read value is always "1".
296 chapter 11 a/d converter 11.3.3 a/d data register (adcd) the a/d data register stores the a/d conversion result for the a/d conversion function. n a/d data register (adcd) figure 11.3-6 a/d data register (adcd) m for a/d conversion function the conversion result is decided approximately 44 instruction cycles after a/d conversion is activated. the data of conversion is stored in this register. the value of the register is indeterminate while a/d conversion is in progress. the register is read-only for the a/d conversion function. m for sense function before activating the sense function, set the data corresponding to the voltage to be compared (compare voltage). as the register is write-only when the sense function is selected, bit manipulation instructions cannot be used. confirm operation stopped (adc2: ext = "0", adc1: admv = "0") before writing to this register. n example of adcd register setting for sense function condition: av cc = avr = 5.0 v, av ss = 0.0 v r: read- only w: write-only : unused x: indeterminate address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 002f h xxxxxxxx b rrrrrrrr for the a/d conversion function wwwwwwww for the sense function table 11.3-3 example of adcd register setting for sense function compare voltage (v) 5.04.03.02.01.00.0 acdc register set value ff h cd h 9a h 66 h 33 h 00 h
297 11.4 a/d converter interrupts 11.4 a/d converter interrupts the a/d converter has the following two interrupts: ? conversion completion for the a/d conversion function ? match of the input voltage and the comparison condition n interrupt for a/d conversion function when a/d conversion completes, the interrupt request flag bit (adc1: adi) is set to "1". at this time, an interrupt request (irqb) to the cpu is generated if the interrupt request enable bit is enabled (adc2: adie = "1"). write "0" to the adi bit in the interrupt processing routine to clear the interrupt request. the adi bit is set after completion of a/d conversion, regardless of the adie bit value. note: an interrupt request is generated immediately if the adi bit is "1" when the adie bit is changed from disabled to enabled ("0" --> "1"). n interrupt for sense function when the specified comparison condition is satisfied after completion of comparison of the input voltage and compare voltage, the interrupt request flag bit (adc1: adi) is set to "1". at this time, an interrupt request (irqb) to the cpu is generated if the interrupt request enable bit is enabled (adc2: adie = "1"). write "0" to the adi bit in the interrupt processing routine to clear the interrupt request. the adi bit is set when the comparison condition is satisfied, regardless of the adie bit value. note: an interrupt request is generated immediately if the adi bit is "1" when the adie bit is changed from disabled to enabled ("0" --> "1"). n register and vector table for a/d converter interrupt reference: see section 3.4.2 "interrupt processing" for details on the operation of interrupt. table 11.4-1 register and vector table for a/d converter interrupt interrupt interrupt level settings register vector table address register setting bits upper lower irqb ilr3 (007e h ) lb1 (bit 7) lb0 (bit 6) ffe4 h ffe5 h
298 chapter 11 a/d converter 11.5 operation of a/d converter the a/d conversion and sense functions of the a/d converter can be activated by software or can be activated continuously. n activating a/d conversion function m software activation figure 11.5-1 "a/d conversion function (software activation) settings" shows the settings required for software activation of the a/d conversion function. figure 11.5-1 a/d conversion function (software activation) settings on activation, the a/d converter starts the operation of the a/d conversion function. the a/d conversion function can be reactivated while conversion is in progress. m continuous activation figure 11.5-2 "a/d conversion function (continuous activation) settings" shows the settings required for continuous activation of the a/d conversion function. figure 11.5-2 a/d conversion function (continuous activation) settings when continuous activation is enabled, the rising edge of the selected input clock activates the a/d conversion, starting operation of the a/d conversion function. when continuous activation is disabled (adc2: ext = "0"), continuous activation halts but software activation is available. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adc1 ans3 ans2 ans1 ans0 adi admv sifm ad 0 1 adc2 adck adie admd ext resv 001 adcd stores the a/d conversion result. : used bit : unused bit 1 : set "1". 0 : set "0". bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adc1 ans3 ans2 ans1 ans0 adi admv sifm ad 0 adc2 adck adie admd ext resv 011 adcd stores the a/d conversion value. : used bit : unused bit 1 : set "1". 0 : set "0".
299 11.5 operation of a/d converter n operation of a/d conversion function the following describes the operation of the a/d converter. from activation to completion of a/d conversion requires approximately 44 instruction cycles. 1. on activation, a/d conversion sets the conversion-in-progress flag bit (adc1: admv = "1") and connects the sample hold circuit to the specified analog input pin. 2. the internal sample hold capacitor captures the voltage at the analog input pin for approximately 8 instruction cycles. the capacitor holds the voltage until the a/d conversion completes. 3. the comparator compares the voltage captured by the sample hold capacitor with the a/d converter reference voltage starting from the most significant bit (msb) and ending with the least significant bit (lsb), and transfers each bit sequentially to the adcd register. 4. when the complete result has been transferred to the adcd register, the conversion-in- progress flag bit is cleared (adc1: admv = "0") and the interrupt request flag bit is set (adc1: adi = "1"). n activating sense function m software activation figure 11.5-3 "sense function (software activation) settings" shows the settings required for software activation of the sense function. figure 11.5-3 sense function (software activation) settings on activation the sense function starts the operation of the sense function. m continuous activation figure 11.5-4 "sense function (continuous activation) settings" shows the settings required for continuous activation of the sense function. figure 11.5-4 sense function (continuous activation) settings when continuous activation is enabled, the rising edge of the selected input clock activates the bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adc1 ans3 ans2 an s1 ans0 adi admv sifm ad 0 adc2 adck adie admd ext resv 101 adcd sets the compare voltage. : used bit : unused bit 1 : set "1". 0 : set "0". 1 bit 7 bit 6 bit 5 bit 4 bit 3bit 2bit 1bit 0 adc1 ans3 ans2 ans1 ans0 adi admv sifm ad 0 adc2 adck adie admd ext resv 111 adcd sets the compare voltage. : used bit : unused bit 1 : set "1". 0: set "0".
300 chapter 11 a/d converter sense function, starting operation of the sense function. when continuous activation is disabled (adc2: ext = "0"), continuous activation stops but software activation is available. n operation of sense function the following describes the operation of the sense function. from activation to completion of the sense function requires approximately 12 instruction cycles. 1. on activation, the sense function sets the conversion-in-progress flag bit (adc1: admv = "1") and connects the sample hold circuit to the specified analog input pin. 2. the internal sample hold capacitor captures the voltage at the analog input pin for approximately 8 instruction cycles. the capacitor holds the voltage until the comparison completes. 3. the comparator compares the voltage captured by the sample hold capacitor with the voltage corresponding to the value set in the adcd register. 4. when voltage comparison completes, the interrupt request flag bit is set (adc1: adi = "1") if the input voltage matches the condition specified by the compare condition setting bit (adc1: sifm). the adi bit does not change if the input voltage does not match the specified condition or if the input voltage and set voltage are equal. note: for the sense function, an interrupt request is not generated when comparison completes if the comparison condition is not matched. whether or not comparison has completed can be determined by checking whether the conversion-in-progress flag bit (adc1: admv) is "0".
301 11.6 notes on using a/d converter 11.6 notes on using a/d converter this section lists points to note when using the a/d converter. n notes on using a/d converter m input impedance of analog input pins the a/d converter contains a sample hold circuit as shown in figure 11.6-1 "analog input equivalent circuit" to fetch analog input voltage into the sample hold capacitor for eight instruction cycles after activating a/d conversion (or the sense function). for this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. therefore, it is recommended to keep the output impedance of the external circuit low (below 10 k w ). note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1f for the analog input pin. figure 11.6-1 analog input equivalent circuit m notes on setting by program ? for the a/d conversion function, the adcd register maintains previous value until the next a/d conversion is activated. however, the content of the adcd register becomes indeterminate immediately after activating a/d conversion. ? do not re-select the analog input channel (adc1: ans3 to ans0) or do not switch between the a/d conversion and sense functions (adc2: admd) while the a/d conversion or sense function is operating. particularly, when continuous activation is enabled, only perform such operations after disabling continuous activation (adc2: ext = "0") and waiting for the conversion-in-progress flag bit (adc1: admv) to go to "0". stop operation before modifying the compare condition setting bit (adc1: sifm) in the same way when the sense function is operating. ? when using the sense function, stop operation before writing to the adcd register. ? clear the interrupt request flag bit (adc1: adi = "0") before switching between the a/d conversion and sense functions. ? a reset or activation of stop mode stops the a/d converter and initializes all registers. ? interrupt processing cannot return if the interrupt request flag bit (adc1: adi) is "1" and the interrupt request enable bit is enabled (adc2: adie = "1"). always clear the adi bit. mb89620160/160a series sample hold circuit r = 6 k c = 33 pf comparator controller close for 8 instruction cycles after activating a/d conversion. analog channel selector an0 to an3
302 chapter 11 a/d converter m note on interrupt requests the interrupt request flag bit (adc1: adi) is not set if a/d conversion is reactivated (adc1: ad = "1") at the same time as the previous a/d conversion completes, or if the sense function is reactivated (adc1: ad = "1") at the same time as the comparison condition is satisfied. m error the smaller the avr - avss, the greater the error would become relatively. m turn-on sequence for a/d converter power supply and analog inputs always apply the a/d converter power supply (av cc , av ss ) and analog inputs (an0 to an3) at the same time or after turning on the digital power supply (v cc ). similarly, when power supply is turned off, always turn off the a/d converter power supply (av cc , av ss ) and analog inputs (an0 to an3) at the same time or before turning off the digital power supply (v cc ). take care that av cc , av ss , and the analog inputs do not exceed the digital power supply voltage when turning the a/d converter power supply on or off. m conversion time a/d conversion function conversion time and sense function comparison time are affected by the clock mode, oscillator frequency, and main clock speed (speed shift function). m continuous activation input clock the 8/16-bit timer/counter output, which can be selected for continuous activation (adc2: ext = 1), is affected by the clock mode and speed shift function. the timebase timer output, which can also be selected, is not affected by the speed shift function, but the timebase timer output cannot be used in subclock mode because the main clock (which drives the timebase timer) is stopped in that mode. note also that the cycle time is affected (for one cycle) when the timebase timer is cleared.
303 11.7 program example for a/d converter 11.7 program example for a/d converter this section gives program examples for the a/d conversion and sense functions of the 8-bit a/d converter. n program example for a/d conversion function m processing description ? performs software-activated a/d conversion of the analog voltage input to the an0 pin. the example does not use interrupts and detects conversion completion within the program loop. m coding example pdr5 adc1 adc2 adcd equ equ equ equ 000fh 002dh 002eh 002fh ; port 5 data register ; a/d control register 1 ; a/d control register 2 ; a/d data register an0 adi admv ad ext equ equ equ equ equ pdr5:0 adc1:3 adc1:2 adc1:0 adc2:1 ; define the an0 analog input pin. ; define the interrupt request flag bit. ; define the conversion-in-progress flag bit. ; a/d converter activation bit (software activation) ; define the continuous activation enable bit. ;---------- main program ---------------------------------------------------------------------------------------------- cseg ; [code segment] : setb clri clrb an0 ext ; set p50/an0 pin as an analog input pin (an0). ; disable interrupts. ; disable continuous activation. ad_wait bbs mov mov seti : setb admv,ad_wait adc1,#00000000b adc2,#00000001b ad ; loop to check that the a/d converter is stopped. ; select analog input channel 0 (an0), clear interrupt request flag, and do not activate by software. ; disable interrupt request output, select the a/d conversion function, and select software activation by the ad bit. ; enable interrupts. ; activate by software
304 chapter 11 a/d converter n program example for sense function m processing description ? generate an interrupt if the analog voltage input to the an0 pin is less than 3.0 v. ? perform continuous activation of the sense function synchronized with pulses (timebase timer output (from divided by f ch 2 8 ). ? for analog power supply voltage (av cc ) = reference voltage (avr) = 5.0 v, an adcd register value of 0a9h gives a compare voltage of 3.0 v. with a main clock oscillator frequency of 4.2 mhz, the continuous activation cycle time would be 2 8 /4.2 mhz = approx. 61.0 s. m coding example ad_conv bbs clrb mov : : ends admv,ad_conv adi a,adcd ; loop to delay until a/d conversion completes (approx. 41.9 s /4.2 mhz). ; clear interrupt request flag. ; read a/d conversion data. ;------------------------------------------------------------------------------------------------------------ end pdr5 adc1 adc2 adcd equ equ equ equ 000fh 002dh 002eh 002fh ; port 5 data register ; a/d control register 1 ; a/d control register 2 ; a/d data register an0 adi admv ad ext equ equ equ equ equ pdr5:0 adc1:3 adc1:2 adc1:0 adc2:1 ; define the an0 analog input pin. ; define the interrupt request flag bit. ; define the conversion-in-progress flag bit. ; a/d converter activation bit (software activation) ; define the continuous activation enable bit. ilr3 equ 007eh ; set interrupt level setting register. int_v irqb int_v dseg org dw ends abs 0ffe8h wari ; [data segment] ;---------- main program ---------------------------------------------------------------------------------------------- cseg ; [code segment] ; stack pointer (sp) etc. are already initialized.
305 11.7 program example for a/d converter : setb clri mov clrb an0 ilr3,#01111111b ext ; set p50/an0 pin as an analog input pin. ; disable interrupts. ; set interrupt level (level 1). ; disable continuous activation. ad_wait bbs mov mov mov seti admv,ad_wait adcd,#9ah adc1,#00000000b adc2,#00001111b ; loop to check that the a/d converter is halted. ; set compare voltage data (3.0 v). ; select analog input channel 0 (an0), clear interrupt request flag, set compare condition (interrupt if the input voltage is lower), and do not activate by software. ; select timebase timer output as a/d clock, enable interrupt request output, select the sense function, and enable continuous activation. ; enable interrupts. ;---------- interrupt processing routine ---------------------------------------------------------------------------- wari clrb pushw xchw pushw adi a a,t a ; clear interrupt request flag. : user processing : popw xchw popw reti ends a a,t a ;---------------------------------------------------------------------------------------------------------------------------- end
306 chapter 11 a/d converter
307 chapter 12 watch prescaler this chapter describes the functions and operation of the watch prescaler. 12.1 "overview of watch prescaler" 12.2 "block diagram of watch prescaler" 12.3 "watch prescaler control register (wpcr)" 12.4 "watch prescaler interrupt" 12.5 "operation of watch prescaler" 12.6 "notes on using watch prescaler" 12.7 "program example for watch prescaler"
308 chapter 12 watch prescaler 12.1 overview of watch prescaler the watch prescaler provides interval timer functions. four different interval times can be selected. the watch rescaler uses a 15-bit free-run counter which counts-up in sync with a subclock generated by the clock generator. n interval timer function (watch interrupt) ? the interval timer function generates repeated interrupts at fixed intervals with the subclock used as the count clock. ? interrupts are generated by watch prescaler interval timer divided clock outputs. ? the interval timer divided clock output (interval time) can be selected from different settings. ? the watch prescaler counter can be cleared. table 12.1-1 "watch prescaler interval time" lists the available interval times for the watch prescaler. f cl : subclock source oscillation the values enclosed in parentheses ( ) are for a 32.768 khz subclock source oscillation. check: the watch prescaler cannot be used in devices in which a single clock option has been selected. n clock supply function the watch prescaler has the following clock supply functions: ? the timer output used for the subclock oscillation stabilization delay time (one value) ? the clock used for the watchdog timer (one value) ? the clock used for the buzzer output (three values) table 12.1-2 "clocks supplied by watch prescaler" lists the cycles of the clocks that the watch prescaler supplies to various peripherals. table 12.1-1 watch prescaler interval time subclock cycle time interval time 1/f cl (approx. 30.5 m s) 2 10 /f cl (31.25 ms) 2 13 /f cl (0.25 s) 2 14 /f cl (0.50 s) 2 15 /f cl (1.00 s)
309 12.1 overview of watch prescaler f cl : subclock source oscillation the values enclosed in parentheses ( ) are for a 32.768 khz subclock source oscillation. note: the oscillation stabilization delay time should be used as a guideline since the oscillation cycle is unstable immediately after oscillation starts. table 12.1-2 clocks supplied by watch prescaler subclock destination subclock cycle remarks subclock oscillation stabilization delay time 2 15 /f cl (1.00 s) do not switch to the subclock mode during the oscillator stabilization wait time. watchdog timer 2 14 /f cl (0.50 s) count-up clock for the watchdog timer buzzer output 2 3 /f cl to 2 5 /f cl (approx. 0.24 to 0.98 ms) see chapter 15 "buzzer output".
310 chapter 12 watch prescaler 12.2 block diagram of watch prescaler the watch prescaler consists of the following four blocks: ? watch prescaler counter ? counter clear circuit ? interval timer selector ? watch prescaler control register (wpcr) n block diagram of watch prescaler figure 12.2-1 block diagram of watch prescaler m watch prescaler counter a 15-bit up-counter that uses the subclock source oscillation clock as its count clock. m counter clear circuit in addition to being cleared by setting the wpcr register (wclr = "0"), the counter is cleared when the device changes to sub-stop mode (stbc : stp = "1") and by power-on reset (optional). wif wie CCC CCC CCC ws1 ws0 wclr wpcr 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 01234567891011121314 (0.25s) (0.5s) (1.0s) (31.25s) timeclock prescaler counter to buzzer output to watchdog timer f cl watchdog timer clear interval timer selector to clock controller for the oscillation stabilization delay time selector counter clear circuit power-on reset stop mode start (in subclock mode) irq8 (timeclock interrupt) f cl : subclock source oscillation the cycle enclosed in parentheses ( ) is for a 32.768 khz subclock oscillation. wpcr
311 12.2 block diagram of watch prescaler m interval timer selector this circuit selects one of four divided clock outputs of the watch prescaler counter as the interval timer output. the falling edge of the selected output is the event that triggers the watch interrupt. m wpcr register the wpcr register is used to select the interval time bit, clear the counter, control interrupts, and check the state of the watch prescaler.
312 chapter 12 watch prescaler 12.3 watch prescaler control register (wpcr) the watch prescaler control register (wpcr) is used to select the interval timer bit, clear the counter, control interrupts, and check state of the watch prescaler. n watch prescaler control register (wpcr) figure 12.3-1 watch prescaler control register (wpcr) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 000b h wif wie ws1 ws0 wclr 00---000 b r/w r/w r/w r/w r/w wclr watch prescaler clear bit read write 0 clears the watch prescaler 1 reading always return "1". no effect. the bit does not change. ws1 ws0 watch interrupt interval time select bits 0 0 2 10 /f cl 01 2 13 /f cl 10 2 14 /f cl 11 2 15 /f cl wie interrupt request enable bit 0 disables interrupt request output 1 enables interrupt request output wif watch interrupt request flag bit read write 0 have no interval interrupt clears this bit. 1 have interval interrupt no effect. the bit does not change. r/w : readable and writable w : write-only : unused x : indeterm inate : initial value
313 12.3 watch prescaler control register (wpcr) table 12.3-1 watch prescaler control register (wpcr) bits bit function bit 7 wif: watch interrupt request flag bit ? set to "1" by the falling edge of the selected interval timer divided output. ? an interrupt request is output when both this bit and the interrupt request enable bit (wie) are "1". ? writing "0" clears this bit. writing "1" has no effect and does not change the bit value. bit 6 wie: interrupt request enable bit ? this bit enables or disables an interrupt request output to the cpu. an interrupt request is output when both this bit and the watch interrupt request flag bit (wif) are "1". bit 5 bit 4 bit 3 unused bits ? the read value is indeterminate. ? writing to these bits has no effect on the operation. bit 2 bit 1 ws1, ws0: watch interrupt interval time selection bits ? select interval timer cycle. ? specify which bit of the watch prescaler counter (or which divided output) will be used for the interval timer. ? one of four interval times may be selected. bit 0 wclr: watch prescaler clear bit ? bit used to clear the watch prescaler counter. ? writing "0" to this bit clears the counter to 0000 h . writing "1" has no effect and does not change the bit value. note: the read value is always "1".
314 chapter 12 watch prescaler 12.4 watch prescaler interrupt the watch prescaler generates an interrupt request at the falling edge of the specific divided output (interval timer function). n interrupts for interval timer function (watch interrupt) the watch prescaler counter counts up, clocked by the subclock source oscillation. unless the system is in main-stop mode, the watch interrupt request flag is set to "1" (wpcr: wif = 1) at the end of the selected time interval. at this time, an interrupt request (irq8) to the cpu is generated if the interrupt request enable bit is enabled (wpcr: wie = "1"). write "0" to the wif bit in the interrupt processing routine to clear the interrupt request. the wif bit is set when the specified divide output falls, regardless of the wie bit value. check: when enabling an interrupt request output (we = "1") after wake-up from a reset, always clear the wif bit (wif = "0") at the same time. notes: an interrupt request is generated immediately if the wif bit is "1" when the wif bit is changed from disabled to enabled ("0" --> "1"). the wif bit is not set if the counter cleared (wpcr: wclr = "0") at the same time as an overflow on the specified bit occurs. n oscillation stabilization delay time and watch interrupt if the interval time is set shorter than the subclock oscillation stabilization delay time, an watch interrupt request from the watch prescaler (wpcr: wif ="1") is generated at the time when cpu wakes up from sub-stop mode by an external interrupt. in this case, disable the watch prescaler interrupt (wpcr: wie = "0") when changing to sub-stop mode. n register and vector table for watch prescaler interrupt table 12.4-1 "register and vector for watch prescaler interrupt" lists the register and vector table for watch prescaler interrupt. reference: see section 3.4.2 "interrupt processing" for details on the interrupt operations. table 12.4-1 register and vector for watch prescaler interrupt. interrupt interrupt level settings register vector table address register setting bits upper lower irq8 ilr3 (007e h ) l81 (bit 1) l80 (bit 0) ffea h ffeb h
315 12.5 operation of watch prescaler 12.5 operation of watch prescaler the watch prescaler has the interval timer function and the clock supply function. n operation of interval timer function (watch prescaler) figure 12.5-1 "interval timer function settings" shows the settings required to operate the interval timer function. figure 12.5-1 interval timer function settings provided the subclock is oscillating, the watch prescaler 15-bit counter (continues to count-up using the subclock as its count clock). after being cleared (wclr = "0"), the counter restarts counting-up from "0000 h ". when the counter reaches a full count of "7fff h ", the next count takes it "0000 h " and it continues to count-up. as the count proceeds, a falling edge will eventually occur at the selected divided clock output. at this time, unless the system is in main clock stop mode, the watch prescaler sets the watch interrupt request flag bit (wif) to "1". consequently, the watch prescaler generates interrupt requests at fixed intervals (the selected interval time), based on the time that the counter is cleared. n operation of clock supply function the watch prescaler is also used as a timer to generate the subclock oscillation stabilization delay time. the time between the counter cleared state and the falling edge of the msb output is used the subclock oscillation stabilization delay time (2 15 /f cl , where f cl is subclock source oscillation). the watch prescaler also provides the clock for the watchdog timer. when the watch prescaler is selected as the clock source for the watchdog timer (wdtc: cs = 1) both counters are cleared simultaneously. n operation of watch prescaler figure 12.5-2 "operation of watch prescaler" shows counter states when the interval timer is operating in subclock mode and the system goes into the sleep and stop modes, and when there is a counter clear request. bit 7bit 6bit 5bit 4b it 3 bit 2 bit 1 bit 0 wpcr wif wie ws 1 ws0 wclr 01 0 : used bit 1 : set "1" 0 : set "0"
316 chapter 12 watch prescaler figure 12.5-2 operation of watch prescaler 7fff h 0000 h counter value cleared by changing to sub-stop mode. subclock oscillation stabilization delay time interval cycle subclock oscillation stabilization delay time counter clear (wpcr: wclr = 0) power-on reset (optional) cleared by the interrupt processing routine. wif bit wie bit slp bit (stbc register) subclock sleep mode stp bit (stbc register) wake-up from sleep irq8 sub-stop mode wake-up from stop mode b y an external interrupt for the case when the interrupt interval time selection bits in the watch prescaler control register (wpcr: ws1, ws0) are "set to 11" (2 15 /f cl ) .
317 12.6 notes on using watch prescaler 12.6 notes on using watch prescaler this section lists points to note when using the watch prescaler. the watch prescaler cannot be used in devices in which the single-clock option has been selected. n notes on using watch prescaler m notes on setting bits by program the system cannot recover from interrupt processing if the interrupt request flag bit (wpcr : wie) is "1" and the interrupt request enable bit is enabled (wpcr: wie = "1"). always clear the wif bit. m clearing watch prescaler in addition to being cleared by the watch prescaler clear bit (wpcr: wclr = "0"), the watch prescaler is cleared wherever the subclock oscillation stabilization delay time is required. when the watch prescaler is selected as a count clock of the watchdog timer (wdtc: cs = "1"), clearing the watch prescaler also clears the watchdog timer. m using as timer for oscillator stabilization delay time as the subclock source oscillation is stopped when the power is turned on and during sub-stop mode, the watch prescaler provides the oscillation stabilization delay time after the oscillator starts. do not switch clock modes from main clock to subclock during this delay time (immediately after power on, etc.) the subclock oscillation stabilization delay time is fixed. reference: see section 3.6.5 "oscillation stabilization delay time" for details. m notes on watch interrupt in main-stop mode, the watch prescaler counter operates, but no interrupt request interrupt requests are generated. m notes on peripheral functions that provides a clock supply from watch prescaler as the clock derived from the watch prescaler restarts output from the its initial state when the watch prescaler counter is cleared, the "h" level may be shorter or the "l" level longer by a maximum of half cycle. the clock of the watchdog timer also restarts output from its initial state. however, as the watchdog timer counter is cleared at the same time, the watchdog timer operates in normal cycle.
318 chapter 12 watch prescaler 12.7 program example for watch prescaler this section gives program example for the watch prescaler. n program example for the watch prescaler m processing description generates repeated watch interrupts at 2 15 /f cl (f cl = subclock source oscillation) intervals. at this time, the interval time is 1 second (at 32,768 khz operation). m coding example wpcr wif ilr3 int_v irq8 int_v equ equ equ dseg org dw ends 000bh wpcr:7 007eh abs 0ffeah wari ; address of watch prescaler control register ; define the watch interrupt request flag bit. ; address of the interrupt level setting register 2 ; [data segment] ; set interrupt vector. ;---------- main program ---------------------------------------------------------------------------------------------- cseg ; [code segment] ; stack pointer (sp) etc. are already initialized. : clri mov mov seti : ilr3,#11111110b wpcr,#01000110b ; disable interrupts. ; set interrupt priority (level 2). ; clear interrupt request flag, enable interrupt request output, select 215/fcl, and clear watch prescaler. ; enable interrupts. ;---------- interrupt program ----------------------------------------------------------------------------------------- wari clrb pushw xchw pushw wif a a,t a ; clear interrupt request flag. : user processing :
319 12.7 program example for watch prescaler popw xchw popw reti ends a a,t a ;---------------------------------------------------------------------------------------------------------------------------- end
320 chapter 12 watch prescaler
321 chapter 13 remote control generator (6-bit ppg) this chapter describes the functions and operation of the remote control generator. 13.1 "overview of remote control generator" 13.2 "block diagram of remote control generator" 13.3 "structure of remote control generator" 13.4 "operation of remote control generator" 13.5 "notes on using remote control generator" 13.6 "program example for remote control generator"
322 chapter 13 remote control generator (6-bit ppg) 13.1 overview of remote control generator the remote control generator is a 6-bit binary counter that can select one of four clocks as its count clock. both the cycle of the output waveform and its "h" state pulse width can be set, which allows the circuit to be used as a 6-bit ppg. the circuit uses the same output pin as the buzzer output. n remote control generation function ? generates frequencies for use by a remote control unit, and outputs the signal at the rco pin. ? the cycle and "h" state pulse width of the output waveform can be set separately. ? the count clock can be selected from four different internal clocks. ? the frequencies can generate with a cycle among 2 and 2 6 times the count clock cycle. table 13.1-1 "output cycles and "h" pulse width ranges" lists the available range of "h" state pulse widths. t inst : instruction cycle (affected by clock mode, etc.) *: can also output a steady "h" state (100% duty cycle). m calculation example for the remote control generator cycle an "h" width (when a 0.5 tinst clock is selected for count clock cycle) assume a main clock source oscillation (f ch ) of 4.2 mhz, and a 0.5 t inst clock selected for count clock cycle. also assume main clock mode, and the highest clock speed selected from the system clock control register (sycc: scs = cs1 = cs0 = 1). (this makes the instruction cycle time 4/f ch .) then, for the indicated comparison values, the output waveform cycle and "h" state pulse width can be calculated as follows: table 13.1-1 output cycles and "h" pulse width ranges internal count clock cycle output cycle output "h" pulse width* 0.5 t inst 1 t inst to 32 t inst 0.5 t inst to 31.5 t inst 1 t inst 2 t inst to 63 t inst 1 t inst to 62 t inst 8 t inst 16 t inst to 504 t inst 8 t inst to 496 t inst 32 t inst 64 t inst to 2016 t inst 32 t inst to 1984 t inst cycle comparison value = 011110 b (30 clock cycles) pulse width comparison value = 001010 b (10 clock cycles) cycle = (cycle comparison value + 1) count clock cycle = "011110 b " (30+1 clock cycles) 0.5 4/f ch = 31 0.475 m s = 14.725 m s
323 13.1 overview of remote control generator if the "h" pulse width setting is equal to or greater than the cycle setting, the output will be a steady "h" state. m calculation example for the remote control generator cycle an "h" width (when a 1/8/32 tinst clock is selected for count clock cycle) assume a main clock source oscillation (f ch ) of 4.2 mhz, and a 1 t inst clock selected for count clock cycle. also assume main clock mode, and the highest clock speed selected from the system clock control register (sycc: scs = cs1 = cs0 = 1). (this makes the instruction cycle time 4/f ch .) then, for the indicated comparison values, the output waveform cycle and "h" state pulse width can be calculated as follows: if the "h" pulse width setting is equal to or greater than the cycle setting, the output will be a steady "h" state. n 6-bit ppg function (when a 0.5 tinst clock selected for count clock cycle) because the cycle and "h" pulse width of its output waveform can be set separately, the remote control generator can be used as a 6-bit ppg. the duty ratio is from 1.56% to 100%. the valid range of "h" pulse width comparison settings, however, is from "0" to the cycle comparison setting. this means that the lower the cycle comparison setting (the shorter the cycle of the output waveform), the lower the resolution (the larger the minimum duty ratio step size). for a cycle comparison setting of "1", for example, the possible "h" pulse width comparison settings would be "0" and "1" which would result in a resolution of 1/2. the duty ratios for these settings would be 50% and 100%, or a minimum duty ratio step of 50%. the output cycle and duty ratio are calculated as follows: output cycle = (cycle comparison value +1) 0.5 tinst. duty ratio (%) = ("h" pulse width compare value +1 )/(cycle compare value +1) 100 table 13.1-2 "6-bit ppg resolution and output cycles (0.5 tinst count clock)" shows the available output cycle, resolution and the minimum steps for duty ratio. "h" pulse width = ("h" pulse width comparison value + 1) count clock cycle = "001010 b " (10 + 1 clock cycles) 0.5 4/f ch = 11 0.475 m s = 5.225 m s cycle comparison value = 011110 b (30 clock cycles) pulse width comparison value = 001010 b (10 clock cycles) cycle = cycle comparison value count clock cycle = "011110 b " (30 clock cycles) 1 4/f ch = 30 0.95 m s = 28.6 m s "h" pulse width = "h" pulse width comparison value count clock cycle = "001010 b " (10 clock cycles) 1 4/f ch = 11 0.95 m s = 9.5 m s
324 chapter 13 remote control generator (6-bit ppg) table 13.1-2 6-bit ppg resolution and output cycles (0.5 tinst count clock) cycle comparison value "h" pulse width comparison value setting range output cycle resolution duty ratio minimum step count clock = 0.5 t inst 00 - output "h" 1 0 to 1 1 t inst 1/2 50.0%* 2 0 to 2 1.5 t inst 1/3 33.3%* 3 0 to 3 2.0 t inst 1/4 25.0%* 4 0 to 4 2.5 t inst 1/5 20.0%* 5 0 to 5 3.0 t inst 1/6 16.7%* 6 0 to 6 3.5 t inst 1/7 14.3%* 7 0 to 7 4.0 t inst 1/8 12.5%* 8 0 to 8 4.5 t inst 1/9 11.1%* 9 0 to 9 5.0 t inst 1/10 10.0%* 10 0 to 10 5.5 t inst 1/11 9.09%* : 15 0 to 15 8.0 t inst 1/16 6.25%* : 20 0 to 20 10.5 t inst 1/21 4.76%* : 25 0 to 25 13.0 t inst 1/26 3.85%* : 30 0 to 30 15.5 t inst 1/31 3.23%* : 40 0 to 40 20.5 t inst 1/41 2.44%* : 50 0 to 50 25.5 t inst 1/51 1.96%* : 60 0 to 60 30.5 t inst 1/61 1.64%* : 63 0 to 63 32 t inst 1/64 1.56%* t inst : instruction cycle time
325 13.1 overview of remote control generator n 6-bit ppg function (when a 1/8/32 tinst clock selected for count clock cycle) because the cycle and "h" pulse width of its output waveform can be set separately, the remote control generator can be used as a 6-bit ppg. the duty ratio is from 1.6% to 100%. the valid range of "h" pulse width comparison settings, however, is from "1" to the cycle comparison setting. this means that the lower the cycle comparison setting (the shorter the cycle of the output waveform), the lower the resolution (the larger the minimum duty ratio step size). for a cycle comparison setting of "2", for example, the possible "h" pulse width comparison settings would be "1", and "2", which would result in a resolution of 1/2. the duty ratios for these settings would be 50%, and 100%, or a minimum duty ratio step of 50%. output cycle = cycle comparison value selected count clock cycle duty ratio (%) = ("h" pulse width compare value/cycle compare value) 100 table 13.1-3 "6-bit ppg resolution and output cycles (0.5 tinst count clock)" shows the available output cycle, resolution and the minimum steps for duty ratio. *: steady "h" output when "h" pulse width comparison value is equal to period comparsion value. table 13.1-3 6-bit ppg resolution and output cycles (0.5 tinst count clock) cycle comparison value "h" pulse width comparison value setting range output cycle (count clock) resolution duty ratio minimum step 1 t inst 8 t inst 32 t inst 0 0 prohibited setting output "h" 11 2 1 to 2 2 t inst 16 t inst 64 t inst 1/2 50.0%* 3 1 to 3 3 t inst 24 t inst 96 t inst 1/3 33.3%* 4 1 to 4 4 t inst 32 t inst 128 t inst 1/4 25.0%* 5 1 to 5 5 t inst 40 t inst 160 t inst 1/5 20.2%* 6 1 to 6 6 t inst 48 t inst 192 t inst 1/6 16.7%* 7 1 to 7 7 t inst 56 t inst 224 t inst 1/7 14.3%* 8 1 to 8 8 t inst 64 t inst 256 t inst 1/8 12.5%* 9 1 to 9 9 t inst 72 t inst 288 t inst 1/9 11.1%* 10 1 to 10 10 t inst 80 t inst 320 t inst 1/10 10.0%* : 15 1 to 15 15 t inst 120 t inst 480 t inst 1/15 6.7%* : 20 1 to 20 20 t inst 160 t inst 640 t inst 1/20 5.0%* : 25 1 to 25 25 t inst 200 t inst 800 t inst 1/25 4.0%*
326 chapter 13 remote control generator (6-bit ppg) : 30 1 to 30 30 t inst 240 t inst 960 t inst 1/30 3.3%* : 40 1 to 40 40 t inst 320 t inst 1280 t inst 1/40 2.5%* : 50 1 to 50 50 t inst 400 t inst 1600 t inst 1/50 2.0%* : 60 1 to 60 60 t inst 480 t inst 1920 t inst 1/60 1.7%* : 63 1 to 63 63 t inst 504 t inst 2016 t inst 1/63 1.6%* table 13.1-3 6-bit ppg resolution and output cycles (0.5 tinst count clock) cycle comparison value "h" pulse width comparison value setting range output cycle (count clock) resolution duty ratio minimum step 1 t inst 8 t inst 32 t inst t inst : instruction cycle time *: if "h" pulse width comparison setting is "00 h ", a 0.5 tinst long "h" pulse will be outputted. steady "h" output when "h" pulse width comparison value is equal to period comparsion value.
327 13.2 block diagram of remote control generator 13.2 block diagram of remote control generator the remote control generator consists of the following five blocks: ? count clock selector ? 6-bit counter ? comparator circuit ? remote control register 1 (rcr1) ? remote control register 2 (rcr2) n block diagram of remote control generator figure 13.2-1 block diagram of remote control generator rcr2 rcen scl5 scl4 scl3 scl2 scl1 scl0 internal data bus rcr1 rck1 rck0 hsc5 hsc4 hsc3 hsc2 hsc1 hsc0 1 t inst count clock selector 2 1 8 32 6-bit counter clk clear comparator circuit 6 6 internal data bus period comparison value remote control transmit output enable signal "h" pulse width comparison value pin p24/rco remote control transmit output t inst : instruction c ycle
328 chapter 13 remote control generator (6-bit ppg) m count clock selector selects a count-up clock for the 6-bit counter from the four available internal count clock. m 6-bit counter the 6-bit counter counts-up, on the count clock selected by the count clock selector. the counter can be cleared by clearing the output enable bit of the rcr2 register (rcr2: rcen = 0). m comparison circuit the comparison circuit holds a "h" state until the count in the 6-bit counter matches the setting in the "h" pulse width compare register. then it holds the "l" state until the counter count matches the setting in the cycle compare register, at which time the counter is cleared to all zeros and continues counting. m remote control register 1 (rcr1) rcr1 is used to select the counter clock for remote control transmit output, and set the output "h" pulse width comparison value. m remote control register 2 (rcr2) rcr2 is used to enable/disable outputs for remote control transmit output, and set the output cycle comparison value.
329 13.3 structure of remote control generator 13.3 structure of remote control generator the section describes the pin, pin block diagram and register of the remote control generator. n remote control generator pin the remote control generator uses the p24/rco pin. the pin can function as an i/o port (p24), or as the remote control output (rco). rco: when the remote control transmit output enable bit is set to "1" (rcr2: rcen = 1), this pin functions as the remote control transmit output pin, outputting a waveform having a "h" state pulse width and cycle as set. n block diagram of remote control generator pin figure 13.3-1 block diagram of p24/rco pin for mb89983 pdr (port data register) ddr internal data bus pdr read pdr read (for bit manipulation instructions) output latch pdr write ddr write pin spl: pin state specificat ion bit in the standby control register (stbc) n-ch stop, watch mode (spl = 1) (port data direction register) peripheral output peripheral output enable stop, watch mode pull-up resistor (approx. 50 k /5.0 v) r p24/rco
330 chapter 13 remote control generator (6-bit ppg) figure 13.3-2 block diagram of p24/rco pin for mb89p985 and mb89pv980 n remote control generator registers figure 13.3-3 remote control transmit generator registers pdr (port data register) ddr internal data bus pdr read pdr read (for bit manipulation instructions) output latch pdr write ddr write pin spl: pin state specification bit in the standby control register (stbc) n-ch stop, watch mode (spl = 1) (port data direction register) peripheral output peripheral output enable stop, watch mode p24/rco rcr1 (remote control register 1) rcr2 (remote control register 2) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0014 h rck1 rck0 hsc5 hsc4 hsc3 hsc2 hsc1 hsc0 00000000 b r/w r/w r/w r/w r/w r/w r/w r/w address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0015 h rcen scl5 scl4 scl3 scl2 scl1 scl0 0-000000 b r/w r/w r/w r/w r/w r/w r/w r. w: readable and writable : unused
331 13.3 structure of remote control generator 13.3.1 remote control register 1 (rcr1) remote control register 1 is used to select the counter clock, and set the "h" pulse width. n remote control register 1 (rcr1) figure 13.3-4 remote control register 1 (rcr1) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0014 h rck1 rck0 hsc5 hsc 4 hsc3 hsc2 hsc1 hsc0 00000000 b r/w r/w r/w r/w r/w r/w r/w r/w hsc5 to hsc0 "h" pulse width setting bits xxxxxx "h" pulse width comparison value rck1 rck0 count clock selection bits 00 1/2 t inst 01 1 t inst 10 8 t inst 11 32 t inst r/w : reada ble and writable t inst : instruction cy cle
332 chapter 13 remote control generator (6-bit ppg) table 13.3-1 remote control register 1 (rcr1) bits bit function bit 7 bit 6 rck2, rck1: count clock selection bits select one of four internal clocks as the remote control transmit frequency generator count clock. bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hsc5 to hsc0: "h" pulse width setting bits these bits set the number of counts for which the remote control output generator output is to remain "h". (the "h" pulse width comparison value to be matched by the count in the counter.) note: when the count clock is 0.5 tinst the setting value between "000000" and "111110" (00 to 3e h ) is always set a value less than the cycle comparison setting. if they are set equal to or greater than the setting, a steady "h" is output. when the count clock is 1/8/32 tinst the setting value between "000001" and "111110" (01 to 3e h ) is always set a value less than the cycle comparison value. if the value is set to "000000", a 0.5 tinst long "h" pulse will be outputted. if they are set equal to or greater than the setting, a steady "h" is output.
333 13.3 structure of remote control generator 13.3.2 remote control register 2 (rcr2) remote control register 2 is used to enable/disable outputs, and set the output cycle period. n remote control register 2 (rcr2) figure 13.3-5 remote control register 2 (rcr2) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0015 h rcen scl5 scl4 scl3 scl2 scl1 scl0 0-000000 b r/w r/w r/w r/w r/w r/w r/w scl5 to scl0 cycle setting bits xxxxxx cycle compare value of remote control transmit output rcen output enable bit 0 disable output; clear counter. 1 enable output; start counter. r/w : readable and writable : unused
334 chapter 13 remote control generator (6-bit ppg) table 13.3-2 remote control register 2 (rcr2) bits bit function bit 7 rcen: output enable bit when this bit is "0", the p24/rco pin functions as a n-ch open- drain port pin (p24), and when it is "1", the pin functions as the remote control transmit output pin (rco). setting this bit to "0" clears and stops the counter; setting it to "1" starts the counter. bit 6 unused bits ? the read value is indeterminate. ? writing to this bit has no effect on the operation. bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scl5 to scl0: cycle setting bits these bits set the length of the output cycle in terms of counter counts. (the cycle comparison value to be matched by the count in the counter.) note: when the count clock is 0.5 tinst the setting value is between "000001" and "111111" (01 to 3f h ). the rco output will remain the previous state until the cycle comparison value is matched by the count value in the counter. then the rco output will output "h" state. when the count clock is 1/8/32 tinst the setting value is between "000010" and "111111" (02 to 3f h ). the rco output will remain the previous state until the cycle comparison value is matched by the count value in the counter. then the rco output will output "h" state. if this setting value is set to "01 h " and the "h" pulse comparison value is "00 h ", rco will output a 0.5 tinst long "h" pulse.
335 13.4 operation of remote control generator 13.4 operation of remote control generator the remote control generator (6-bit ppg) generates a remote control transmit output in which the cycle and "h" state pulse width of the output can be set separately. n operation of remote control generator figure 13.4-1 "remote control generator settings" shows the settings required to operate the remote control generator. figure 13.4-1 remote control generator settings when the remote control generator output is enabled, its 6-bit counter starts counting up from "zero" in synchronization with the selected count clock. during the first cycle, the rco pin output will remain in the previous state value until the count in the counter matches the "h" state pulse width comparison value. when this happens, the rco pin goes "l" and stays there until the count matches the cycle period comparison value, at which time the rco pin goes "h" and the 6-bit counter is cleared to zero and continues to count. the fact that the pulse width and period can be set separately enables the circuit to be used as a 6-bit ppg. figure 13.4-2 "operation of remote control generator" shows the operation of the remote control generator after the first rco output cycle. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rcr1 rck1 rck0 hs c5 hsc4 hsc3 hsc2 hsc1 hsc0 rcr2 rcen scl5 scl4 scl3 scl2 scl1 scl0 1 : used bit 1 : set "1". 0 : set "0".
336 chapter 13 remote control generator (6-bit ppg) figure 13.4-2 operation of remote control generator 00 h counter count cycle setting value (rcr2: scl0 to scl5) high pulse width setting value (rcr1: hsc0 to hsc5) period *1 pulse width *2 *1 : when count clock is 0.5 t inst period = 0.5 t inst x (period comparison value + 1) when count clock is 1/8/32 t inst period = count clock period x period comparison value *2: when count clock is 0.5 t inst pulse width = 0.5 t inst x (high pulse width comparison value + 1) when count clock is 1/8/32 t inst pulse width = count clock period x high pulse width comparison value rco waveform
337 13.5 notes on using remote control generator 13.5 notes on using remote control generator this section lists points to note when using the remote control generator. n notes on using remote control generator m "h" pulse width restrictions generally, the "h" pulse width setting bits of remote control register 1 (rcr1: hsc5 to 0) must always be set less than the cycle setting bits of remote control register 2(rcr2: scl5 to 0). for any clock, when scl5 to 0 is "00 h " hsc5 to 0 is equal to scl5:0, or hsc5 to 0 is larger than scl5 to 0, the rco pin will remain a steady "h" level. for any clock, when hsc5 to 0 is "00 h " and scl5 to 0 is not equal to "00 h ", the rco pin will start to output "l" level and then output a 0.5 tinst long "h" pulse after every cycle match is detected. m resolution when count clock is 0.5 t inst , the maximum "h" pulse width resolution is 1/64 of the cycle (the resolution when the cycle setting is "111111" (3f h ). reducing the time of the cycle reduces the resolution, with the minimum resolution of 1/2 occurring with a cycle setting of "000001" (01 h ). when count clock is 1/8/32 t inst , the maximum "h" pulse width resolution is 1/63 of the cycle (the resolution when the cycle setting is "111111" (3f h ). reducing the time of the cycle reduces the resolution, with the minimum resolution of 1/2 occurring with a cycle setting of "000010" (02 h ). m changing settings during operation figure 13.5-1 "changing settings during operation (remote control)" illustrates what happens when settings are changed during remote control generator operation.
338 chapter 13 remote control generator (6-bit ppg) figure 13.5-1 changing settings during operation (remote control) direct comparisons are performed between the 6-bit counter of the remote control generator and the "h" pulse width setting bits (rcr1: hsc5 to hsc0), and between the counter and the cycle setting bits (rcr2: scl5 to scl0). therefore, if a setting is reduced in mid-count, the cycle time (t 1 ) may be long until the counter overflows in the worst case and the takes effect in the next cycle. similarly, the "h" state pulse width (t 2 ) may be long in the worst case until the next end-of-cycle match is detected. m errors activating the counter by program is not synchronized with the start of counting-up using the selected count clock. therefore, the time from activating the counter until a match with the "h" pulse comparison value and cycle comparison value are detected may be shorter than the theoretical time by a maximum of one cycle of the count clock. figure 13.5-2 "error during activating operation (remote control)" shows the error that occurs on starting counter operation. figure 13.5-2 error during activating operation (remote control) *3 *1 *1 *2 00 h *1 3f h counter count overflow cycle setting value (rcr2: scl) "h" pulse width setting value (rcr1: hsc) rco output waveform one cycle *1: since the current count in the counter is less than the new setting, the new setting takes effect for the current cycle. *2: since cycle is changed to a value less than the current count, the counter counts all the way to counter overflow and takes effect in the next cycle (in the worst case). *3: since the new "h" pulse width setting is less that the current count, the pulse width match is not detected until the next cycle (in the worst case). *4: the length of the t 1 and t 2 is depended on when the new cycle setting value and "h" pulse width setting value. it wll vary from case to case. t1*4 t 2* 4 l) one cycle counter activate error cycle for 00 h counter value count clock 00 h 01 h 02 h 03 h 04 h
339 13.6 program example for remote control generator 13.6 program example for remote control generator this section gives a program example for the remote control generator. n programming example for remote control generator m processing description ? generate the remote control transmit output at a cycle of approximately 28.6 s and a 33% duty ratio. ? with a main clock frequency (f ch ) of 4.2 mhz, the highest clock speed (speed shift function), and the 1 tinst clock selected (1 instruction cycle time = 4/f ch ), the comparison value for a cycle of approximately 28.6 m s is as found as follows: cycle comparison value (rcr2: scl5 to scl0) = 28.6 m s/(1 4/4.2 mhz) = 30 ? the comparison value for a "h" state pulse width to provide a 33% duty ratio is found as follows: "h" pulse width comparison value (rcr1: hsc5 to hsc0) = 33/100 cycle comparison value = 0.33 30 = 10 (this is an approximately 9.5 m s "h" pulse width.) m coding example rcr1 rcr2 equ equ 0014h 0015h ; remote control register 1 ; remote control register 2 ;---------- main program ------------------------------------------------------------------------ cseg : mov mov : ends rcr1,#01001010b rcr2,#10011110b ; [code segment] ; select 1 tinst count clock, set "h" pulse width comparison ; value ; enable output and start counter, set cycle period, ; comparison value. ;--------------------------------------------------------------------------------------------------- end
340 chapter 13 remote control generator (6-bit ppg)
341 chapter 14 lcd controller/driver this chapter describes the functions and operation of the lcd controller/driver. 14.1 "overview of lcd controller/driver" 14.2 "block diagram of lcd controller/driver" 14.3 "structure of lcd controller/driver" 14.4 "operation of lcd controller/driver" 14.5 "program example for lcd controller/driver"
342 chapter 14 lcd controller/driver 14.1 overview of lcd controller/driver the lcd controller/driver includes 7 bytes of on-chip display data in memory, the contents of which control an lcd display via 14 segment and 4 common outputs. the function can drive an lcd display panel directly, using one of three selectable duty ratios. n lcd controller/driver function the lcd controller/driver function displays the contents of a display data memory directly to the lcd panel (liquid crystal display) by segment and common outputs. ? up to 14 segment outputs (seg0 to seg13) and four common outputs (com0 to com3) may be used. ? built-in display ram: 7 bytes (14 4 bits) ? three selectable duty ratios (1/2, 1/3, and 1/4). not all duty ratios are available with all bias settings, however. ? either the main or subclock can be selected as the drive clock. ? lcd can be driven directly. table 14.1-1 "bias and duty ratio combinations" shows the duty ratios available with each bias setting. o: recommended mode x: do not use check: the 1/2 bias mode cannot be used with devices that have internal voltage boosters (mb89980 series) because it requires an external divider resistor. if p40/seg0 to p47/seg7, p60/seg8 to p65/seg13, p70/com2, and p71/com3 are set as output-only port pins (general-purpose outputs) as a mask option, they cannot be used as lcd segment and common outputs. when p70/com2 and p71/com3 are used as output-only port pins, the 1/3 and 1/4 duty ratio output modes cannot be used. table 14.1-1 bias and duty ratio combinations part number bias 1/2 duty ratio 1/3 duty ratio 1/4 duty ratio mb89980 series 1/2 bias o x x 1/3 bias x o o
343 14.2 block diagram of lcd controller/driver 14.2 block diagram of lcd controller/driver the lcd controller/driver is made up of the eight blocks listed below. functionally, the circuit can be broken into two major sections: the controller section, which generates lcd segment and common signals based on the current contents of display ram, and the driver section, which develops sufficient drive to operate the display. ? lcd control register 1 (lcr1) ? lcd control register 2 (lcr2) ? display ram ? prescaler ? timing controller ? v/i converter ? common output driver ? segment output driver n block diagram of lcd controller/driver figure 14.2-1 block diagram of lcd controller/driver internal bus lcdc control register 1 (lcr1) prescaler timing controller display ram 14 4 bit (7 bytes) f ch /2 7 (timebase timer output) subclock (32 khz) common output driver segment output driver v/i converter 4 14 v0 v1 v2 v3 com0 com1 com2 com3 seg00 seg01 seg02 seg03 seg04 seg9 seg10 seg11 seg12 seg13 : : controller driver 4 lcd control register 2 (lcr2) (only for mb89p985 and mb89pv 980)
344 chapter 14 lcd controller/driver m lcdc control register 1 (lcr1) this register is used to select the frame clock (the clock used to generate the frame cycle), enable/disable operation in watch mode, control the lcd drive supply voltage, select display blanking/non-blanking, select the display mode, and select the lcd clock cycle. m lcdc control register 2 (lcr2) (only for mb89p985 and mb89pv980) this register is used to control port/segment and port/common selection. it is used for mb89p985 and mb89pv980 only. m display ram this 14 4-bit block of ram controls the segment output signals. its contents are automatically read out to the segment outputs in sync with the timing of the selected common signal. m prescaler the prescaler selects settings from 2 clocks and 4 frequencies to generate the frame frequency. m timing controller this block controls the segment and common signals based on the frame frequency and lcr1 register settings. m v/i converter this circuit generates alternating current waveforms from the voltage signals it receives from the timing controller to drive the lcd. m common output driver contains the drivers for the lcd common pins. m segment output driver contains the drivers for the lcd segment pins. m lcd controller/driver supply voltage the lcd driver supply voltage is taken from a voltage divider. the divider can be made up of internal or external resistors connected to the v0 to v3 pins.
345 14.2 block diagram of lcd controller/driver 14.2.1 lcd controller/driver internal divider resistors in devices that have internal divider resistors, the lcd driver supply voltage is taken from an internal voltage divider. (external divider resistors may also be used.) n internal divider resistors devices have internal divider resistors. in these devices, external divider resistors may also be connected at pins v0 through v3. the selection of internal or external resistors is made by the drive supply voltage control bit of lcdc control register 1 (lcr1: vsel). vsel = 1 connects the internal resistors. set vsel to "1" when you want to use the internal resistors only (when no external resistors are connected). the lcdc enable is inactive when lcd operation is stopped (lcr1: ms1 = ms0 = 00 b ), and when operation is stopped (lcr1: lcen = 0) in watch mode (stbc: tmd = 1). pin v2 and v1 should be shorted together when using the 1/2 bias setting. figure 14.2-2 "internal voltage divider equivalent circuit" shows an equivalent circuit of the internal voltage divider. figure 14.2-2 internal voltage divider equivalent circuit vcc v3 v2 v1 v0 n-ch p-ch 2r n-ch p-ch r n-ch p-ch r n-ch p-ch r n-ch v 2 v 1 v 0 v 3 vsel short together when using 1/2 bias. mb89980 series lcdc enable v 0 to v 3 : voltages at v0 to v3 pins.
346 chapter 14 lcd controller/driver n use of internal voltage divider resistors figure 14.2-3 "use of internal voltage divider resistors" shows the voltage divider circuits for 1/ 2 and 1/3 bias. as shown in this figure, in the 1/2 bias mode (with lcdc enabled) v2 and v1 will be 1/2 of v3 (v3 is the lcd operating voltage, which is vcc/2 in this configuration). in the 1/3 bias mode, v1 is 1/3 of v3, and v2 is 2/3 of v3. figure 14.2-3 use of internal voltage divider resistors n display brightness adjustment when internal divider resistors are used when internal divider resistors do not provide sufficient lcd display brightness, connect an external brightness adjust variable resistor between vcc and v3 as shown in figure 14.2-4 "use of internal voltage divider resistors with brightness adjustment". 2r v 3 r v 2 r v 1 r v 0 vcc v3 v2 v1 v0 nch 2r v 3 r v 2 r v 1 r v 0 vcc v3 v2 v1 v0 nch lcdc enable lcdc enable mb89980 series mb89980 series 1/2 bias 1/3 bias v 0 to v 3 : voltages at v0 to v3 pins.
347 14.2 block diagram of lcd controller/driver figure 14.2-4 use of internal voltage divider resistors with brightness adjustment note: during lcd operation, the 2r internal resistance will be in the divider circuit, and vr will be in parallel with this resistor. 2r v 3 r v 2 r v 1 r v 0 vcc v3 v2 v1 v0 nch vr v 0 to v 3 : voltages at v0 to v3 pins. mb89980 series when display brightness adjustment is desired lcdc enable
348 chapter 14 lcd controller/driver 14.2.2 lcd controller/driver external divider resistors external voltage divider resistors can also be used with devices that have internal divider resistors. display brightness can be adjusted by a variable resistor connected between the v cc and v3 pins. n external divider resistors when you are using a device without a voltage booster, but do not wish to use the internal divider resistors, external voltage divider resistors can be connected at the lcd drive voltage supply pins (v0 to v3). figure 14.2-5 "external voltage divider resistor connections" shows connections for external divider resistors for the two biasing modes, and table 14.2-1 "lcd drive voltages and biasing modes" lists the corresponding lcd drive voltages. figure 14.2-5 external voltage divider resistor connections v0 to v3: voltages at pins v0 to v3. v lcd : lcd operating voltage n using external divider resistors internally, the v0 pin is connected through a transistor to v ss (gnd). therefore, when external voltage divider resistors are used, the current flow to the external resistors with the lcd controller off can be cut off by connecting the v ss end of the divider to the v0 pin only. figure 14.2-6 "external voltage divider resistor connections" shows an external voltage divider 1/3 bias vcc v3 v2 v1 v0 vr r r v lcd vcc v3 v2 v1 v0 vr r r v lcd r mb89980 series mb89980 series 1/2 bias 1/3 bias table 14.2-1 lcd drive voltages and biasing modes v3 v2 v1 v0 1/2 bias v lcd 1/2v lcd 1/2v lcd gnd 1/3 bias v lcd 2/3v lcd 1/3v lcd gnd
349 14.2 block diagram of lcd controller/driver resistor connection. figure 14.2-6 external voltage divider resistor connections 1. to preclude the external voltage divider from being affected by the internal divider resistors, the lcdc control register drive voltage control bit (lcr1: vsel) must be written to "0" to isolate it from the entire internal voltage divider. 2. with the internal voltage divider thus isolated, writing the display mode select bits (ms1 and ms0) of the lcr1 register to any state other than "00 b " will turn on the lcdc enable transistor (q1), causing current to flow in the external divider resistors. 3. writing the display mode select bits (ms1 and ms0) to "00 b " will turn off the lcdc enable transistor (q1), and current will stop flowing in the external resistors. note: the resistance of rx in the external divider depends on the lcd used. select an appropriate value. vcc v3 v2 v1 v0 vr rx rx rx 2r nch r r r v 0 v 1 v 2 v 3 lcdc enable mb89980 series v 0 to v 3 : voltages at v0 to v3 pins.
350 chapter 14 lcd controller/driver 14.3 structure of lcd controller/driver this section describes the pins, pin block diagrams, register, and display ram of the lcd controller/driver. n lcd controller/driver pins the lcd controller/driver uses 4 common output pins (com0 to com3), 14 segment output pin (seg0 to seg13) and 4 lcd driving power supply pins (v0 to v3). m com0, com1, p70/com2, and p71/com3 pins p70/com2 and p71/com3 pins can function either as output-only ports (p70 and p71) and lcd common output pins (com2 and com3). the selection, however is made by mask option in mb89983 and by lcd control register 2 (lcr2) in mb89p985 and mb89pv980. check: when the pins are used as lcd common outputs, the corresponding port data register bits (pdr7: bits 0 and 1) should be set to "1" to turn the output transistor "off". (com0 and com1 are dedicated lcd common output pins.) m p40/seg0 to p47/seg7 and p60/seg8 to p65/seg13 p40/seg0 to p47/seg7 and p60/seg8 to p65/seg13 can function either as output-only ports (p40 to p47 and p60 to p65) and lcd segment output pins (seg0 to seg7 and seg8 to seg13). the selection, however is made by mask option in mb89983 and by lcd control register 2 (lcr2) in mb89p985 and mb89pv980. check: when these pins are used as lcd segment outputs, the corresponding port data registers (pdr4 and pdr6) should be set to all "1s" to turn the output transistors off. m v0 to v3 these pins are the lcd driving power supply pins. n block diagrams of lcd controller/driver pin figure 14.3-1 block diagram of lcd controller/driver pin (dedicated common output pins) dedicated common outp ut pins pin com0, com1 common control signal lcd drive voltage (v 3 or v 2 ) lcd drive voltage (v 1 or v 0 ) common control signal v 0 to v 3 : v0 to v3 pin voltages n ch p ch p ch n ch
351 14.3 structure of lcd controller/driver figure 14.3-2 block diagram of lcd controller-driver pin for mb89983 (dual function common/ segment output pins) p-ch pdr (port data register) internal data bus pdr read output latch pdr write pin spl: pin state specification bit in the standby control register (stbc) n-ch stop, watch mode (spl = 1) mask option p40 to p47 p60 to p65 common/segment control signal lcd drive voltage (v 3 or v 2 ) lcd drive voltage (v 1 or v 0 ) common/segment control signal n ch p ch p ch n ch dual function commom/segment output pins pull-up resistor (approx. 50 k /5.0 v) p70/com2, p71/com3, p40/seg0 to p47/seg7, p60/seg8 to p65/se g13
352 chapter 14 lcd controller/driver figure 14.3-3 block diagram of lcd controller-driver pin for mb89p985 and mb89pv980 (dual function common/segment output pins) check: do not select the pull-up resistor option on pins used for common or segment outputs or capacitor connection pins. pdr (port data register) internal data bus pdr read output latch pdr write pin spl: pin state specification bit in the standby control register (stbc) n-ch stop, watch mode (spl = 1) lcr2 common/segment control signal lcd drive voltage (v 3 or v 2 ) lcd drive voltage (v 1 or v 0 ) common/segment control signal n ch p ch p ch n ch dual function commom/segment outp ut pins p70/com2, p71/com3, p40/seg0 to p47/seg7, p60/seg8 to p65/se g13
353 14.3 structure of lcd controller/driver n lcd controller/driver register figure 14.3-4 lcd controller/driver register n lcd controller/driver ram lcd controller/driver has 14 4-bit of internal display ram in which the data used to generate the segment output signals is stored. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0072 h css lcen vsel bk ms1 ms0 fp1 fp0 00010000 b r/w r/w r/w r/w r/w r/w r/w r/ w r/w : readable and writable x : indeterminate lcr1 (lcd control register 1) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0073 h sc3 ls4 ls3 ls2 ls1 0--0000- b r/w r/w r/w r/w r/w lcr2 (lcd control register 2)
354 chapter 14 lcd controller/driver 14.3.1 lcd control register (lcr1) lcd control register 1 (lcr1) is used to select the frame cycle, enable/disable operation in watch mode, control the lcd drive supply voltage, select display blanking/non-blanking, and select the display mode. n lcdc control register 1 (lcr1) figure 14.3-5 lcdc control register 1 (lcr1) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0072 h css lcen vsel bk ms1 ms0 fp1 fp0 00010000 b r/w r/w r/w r/w r/w r/w r/w r/w fp1 fp0 frame cycle selection bits main clock (css=0) subclock (css=1) 0 0 f ch /(2 12 n) (256 hz) f cl /(2 5 n) (256 hz) 01 f ch /(2 13 n) (128 hz) f cl /(2 6 n) (128 hz) 10 f ch /(2 14 n) (64 hz) f cl /(2 7 n) (64 hz) 11 f ch /(2 15 n) (32 hz) f cl /(2 8 n) (32 hz ) ( ) : values for f ch =4.2 mhz, f cl =32.768 khz, and n=4 n : number of time divisions f ch : main cloc k source oscillation f cl : subclock source oscillaion ms1 ms0 display mode selection bits 0 0 stop lcd operation 01 1/2 duty ratio output mode (time division n = 2) 10 1/3 duty ratio output mode (time division n = 3) 11 1/4 duty ratio output mode (time division n = 4) bk display blanking selection bit 0 display unblanked 1 display blanked vsel drive supply voltage control bit 0 external divider resistors used (internal divider resistors isolated) 1 internal divider redidtors used. lcen watch mode operation enable bit 0 stop in watch mode 1 run in watch mode (also) css frame cycle generate clock selection bit 0 main clock 1 subclock r/w : readable and writable w : write only : initial value
355 14.3 structure of lcd controller/driver table 14.3-1 lcdc control register (lcr1) bit functions bit function bit 7 css: frame cycle generation clock selection bit selects the frame clock, which generates the frame cycle for lcd display. "0" selects the output of the timebase timer derived from the main clock divided by f cl 2 7 ; "1" selects the subclock as the frame clock. check: the timebase timer output may not be selected as the frame clock in the main-stop and subclock modes because the main clock oscillator is stopped in those modes. note: when the timebase timer output is selected, the frame clock is not affected when clock speed is changed via the speed shift function. (the timebase timers count clock is not supplied through the speed shift function.) bit 6 lcen: watch mode operation enable bit determines whether the lcd controller/driver will operate in watch mode. if this bit is "1", the lcd display will continues to operate after the system goes to watch mode; if it is "0", the lcd will cease operation. check: to use the display in watch mode, the subclock must be selected as the frame clock (css = 1). bit 5 vsel: lcd drive supply voltage control bit ? in devices that have an internal divider resistor, the vsel bit controls the divider current path continuity. a "1" in this bit completes the divider current path; a "0" opens it. this bit must be "0" when external divider resistors are used. bit 4 bk: display blanking selection bit blanks/unblanks the lcd. setting this bit to "1" (blank) outputs a "deselect" waveform to the lcd segments (which blanks the display). bit 3 bit 2 ms1, ms0: display mode selection bits select one of three output waveform duty ratio modes. the mode selected affects the common pins used. setting both bits to "0" turns "off" the display (stops lcd controller/driver display operation). check: before going to a mode in which the selected frame cycle generate clock oscillator is stopped (stop mode, etc.), these bits should be written to "00 b " to turn off the display. bit 1 bit 0 fp1, fp0: frame cycle selection bits these bits select one of four lcd display frame cycles. check: to determine this register setting, calculate the optimum frame frequency for the lcd module you are using. note that the frame cycle is a function of main clock frequency.
356 chapter 14 lcd controller/driver 14.3.2 lcd control register (lcr2) lcd control register 2 (lcr2) is used to make the port/segment and port/common selection in mb89p985 and mb89pv980 only. in mb89983, the port/segment and port/ common selection is made by mask option, so that it is no need to use this register. n lcd control register 2 (lcr2) figure 14.3-6 lcd control register 2 (lcr2) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0073 h sc3 ls4 ls3 ls2 ls1 0--0000- b r/w r/w r/w r/w r/w ls1 port/segment selection bit port segment 0 p40 to p43 1 seg0 to seg03 ls2 port/segment selection bit port segment 0 p44 to p47 1 seg04 to seg07 ls3 port/segment selection bit port segment 0 p60 to p61 1 seg08 to seg09 ls4 port/segment selection bit port segment 0 p62 to p65 1 seg10 to seg13 sc3 port/common selection bits po rt common 0 p70, p71 1 com2, com3 r/w : readable and writable : not used : initial value
357 14.3 structure of lcd controller/driver table 14.3-2 lcd control register 2 (lcr2) bit functions bit function bit 7 sc3: port/common selection bit ? these bits are selected for an either general output port or commmon output pin for lcd. bit 6 bit 5 unused bits ? the read value is indeterminate. ? writing to this bit has no effect on the operation. bit 4 bit 3 bit 2 bit 1 ls4, ls3, ls2, ls1: port/segment selection bits ? these bits are selected for an either general output port or segment output pin for lcd. bit 0 unused bit ? the read value is indeterminate. ? writing to this bit has no effect on the operation.
358 chapter 14 lcd controller/driver 14.3.3 display ram display ram consists of 14 4-bit (7 bytes) of display data memory used to generate the segment output signals. n display ram and output pins the contents of display ram are automatically read out and output via the segment outputs in sync with the selected common signal timing. a "1" bit is converted to a "select" (display on) voltage and a "0" to a "deselect" (display off) voltage. since the operation of the lcd is not directly related to the operation of the cpu, display ram read/write timing can be set by the user. the seg8 to seg23 pins that are not made dedicated segment outputs by mask option selection may be used as general-purpose output-only port pins, and the ram that goes with those pins may be used as regular ram. (see table 14.3-3 "segment outputs, display ram locations, and sharing port pins".) table 14.3-4 "common outputs and display ram bits used in each duty ratio mode" shows the relationship between duty ratio mode, common outputs, and display ram. figure 14.3-7 "segment/common output pins and corresponding display ram" shows which display ram bits are associated with each segment and common output pin. figure 14.3-7 segment/common output pins and corresponding display ram address 0060 h bit3 bit2 bit1 bit0 seg0 bit7 bit6 bit5 bit4 seg1 0061 h bit3 bit2 bit1 bit0 seg2 bit7 bit6 bit5 bit4 seg3 0062 h bit3 bit2 bit1 bit0 seg4 bit7 bit6 bit5 bit4 seg5 0063 h bit3 bit2 bit1 bit0 seg6 bit7 bit6 bit5 bit4 seg7 0064 h bit3 bit2 bit1 bit0 seg8 bit7 bit6 bit5 bit4 seg9 0065 h bit3 bit2 bit1 bit0 seg10 bit7 bit6 bit5 bit4 seg11 0066 h bit3 bit2 bit1 bit0 seg12 bit7 bit6 bit5 bit4 seg13 com3 com2 com1 com0 pins seg8 to seg13 share pins with port 6 (p60 to p65). pins seg0 to seg7 share pins with port 4 (p40 to p47). ram area and common pins used in 1/2 duty ratio mode ram area and common pins used in 1/3 duty ratio mode ram area and common pins used in 1/4 duty ratio mode
359 14.3 structure of lcd controller/driver note: locations in the display ram area that are not required for display data can be used as regular ram. o: used -: not used *: the lcd common output option must be selected for pins com2 and com3 (mask option). table 14.3-3 segment outputs, display ram locations, and sharing port pins segment/common output pins used (mask option) corresponding display ram area general-purpose ports sharing same pins seg10 to seg13 (4 pins) com0, com1 65 h to 66 h p40 to p47, p60, p61, p70, p71 (10 + 2 pins) seg8 to seg13 (6 pins) com0, com1 64 h to 66 h p40 to p47, p70, p71 (8 + 2 pins) seg4 to seg13 (10 pins) com0, com1 62 h to 66 h p40 to p43, p70, p71 (4 + 2 pins) seg0 to seg13 (14 pins) com0, com1 60 h to 66 h p70, p71 (2 pins) seg10 to seg13 (4 pins) com0 to com3 65 h to 66 h p40 to p47, p60, p61 (10 pins) seg8 to seg13 (6 pins) com0 to com3 64 h to 66 h p40 to p47 (8 pins) seg4 to seg13 (10 pins) com0 to com3 62 h to 66 h p40 to p43 (4 pins) seg0 to seg13 (14 pins) com0 to com3 60 h to 66 h none table 14.3-4 common outputs and display ram bits used in each duty ratio mode duty ratio setting common outputs used display data bit used bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1/2 com0 to com1 (2 pins) - - o o - - o o 1/3* com0 to com2 (3 pins) - o o o - o o o 1/4* com0 to com3 (4 pins) o o o o o o o o
360 chapter 14 lcd controller/driver 14.4 operation of lcd controller/driver the lcd controller/driver provides the necessary control and drive for an lcd display. n operation of lcd controller/driver figure 14.4-1 "lcd controller/driver settings" shows the settings required to operate the lcd display. figure 14.4-1 lcd controller/driver settings once the above settings have been made, if the selected clock for frame cycle generation is running, lcd panel driving waveforms reflecting the contents of display ram will be output at the segment and common output pins (com0 to com3 and seg0 to seg13). although the clock for frame period generation can be switched even while the lcd is displaying data, the display may flicker when the switching occurs. this can be avoided by temporarily blanking the display (lcr1: bk = 1), etc. while switching. the display driving output is a two-frame a.c. waveform for which the bias level and display duty cycle is selected by settings. when the p70/com2 and p71/com3 pins are set as com outputs, deselection levels are output in the waveforms at the com2 and com3 outputs in 1/2 duty ratio operation, and at the com3 output in 1/3 duty ratio operation. when lcd display operation is stopped (lcr1: ms1 = ms0 = 00b), and during reset, all com and seg output pins are taken "l". check: if the selected frame cycle generate clock were to stop while the lcd display is operating, the circuit that converts the waveform from d.c. to a.c. would also stop, causing a d.c. voltage to be applied to the liquid crystal cells. the lcd display must be therefore be stopped before the clock is stopped. the conditions under which the main clock (timebase timer) and subclock are stopped are a function of the clock mode and standby mode. also note that when the timebase timer is selected as the frame clock source (lcr1: css = 0), clearing the timebase timer will affect the frame cycle. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lcr1 css lcen vsel bk ms1 ms0 fp1 fp0 0 display ram 060 h to 06b h display data : used bit 1 : set "1". 0 : set "0". other than "00 h "
361 14.4 operation of lcd controller/driver n lcd driving waveforms it is characteristic of lcds that applying d.c. drive to the panel can cause electrochemical degradation of the material used in the lcd cells. for this reason, the lcd controller/driver includes a circuit to convert the original driving waveform to a two-frame a.c. output waveform (zero d.c. bias) to drive the lcd. there are three types of output waveform: ? 1/2 bias, 1/2 duty ratio output waveform (only devices without voltage boosters) ? 1/3 bias, 1/3 duty ratio output waveform ? 1/3 bias, 1/4 duty ratio output waveform
362 chapter 14 lcd controller/driver 14.4.1 output waveforms during lcd controller/driver operation (1/2 duty ratio) the display drive output is a multiplex drive-type two-frame a.c. waveform. in the 1/2 duty ratio mode, the only common outputs are com0 and com1. (com2 and com3 are not used.) n output waveforms during lcd controller/driver operation (1/2 duty ratio) m 1/2 bias, 1/2 duty output waveform the maximum potential difference exists between a segment output and the corresponding common output when the segment (lcd cell) is "turned on". figure 14.4-2 "output waveforms, 1/2 bias and 1/2 duty ratio example" shows the output waveforms for the display ram contents listed in table 14.4-1 "display ram contents example". -: not used table 14.4-1 display ram contents example segment display ram contents com3 com2 com1 com0 segn - - 0 0 segn+1 - - 0 1
363 14.4 operation of lcd controller/driver figure 14.4-2 output waveforms, 1/2 bias and 1/2 duty ratio example 1 v 3 v 2 =v 1 v 0 =v ss v 3 v 2 =v 1 v 0 =v ss v 3 v 2 =v 1 v 0 =v ss v 3 v 2 =v 1 v 0 =v ss v 3 v 2 =v 1 v 0 =v ss v 3 v 2 =v 1 v 0 =v ss v 3 (on) v 2 v ss -v 2 -v 3 (on) v 3 (on) v 2 v ss -v 2 -v 3 (on) v 3 (on) v 2 v ss -v 2 -v 3 (on) v 3 (on) v 2 v ss -v 2 -v 3 (on) com0 com1 com2 com3 seg n seg n+1 difference in potential between com0 and seg n difference in potential between com1 and seg n difference in potential between com0 and seg n+1 difference in potential between com1 and seg n+1 1 frame 1 cycle v 0 to v 3 : v0 to v3 pin volta g es
364 chapter 14 lcd controller/driver m lcd panel connections and display data example (1/2 duty ratio drive mode) figure 14.4-3 segment/common connections, data states and corresponding display com1 com0 seg n+3 seg n+2 seg n+1 seg n * 7 * 0 * 5 * 4 * 2 * 6 * 1 * 3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 com3 CC CC CC CC CC CC CC CC CC CC CC CC com2 CC CC CC CC CC CC CC CC CC CC CC CC com1 0 1 1 1 0 0 1 1 1 1 0 1 com0 1 1 1 1 0 0 1 0 0 1 1 1 060 h 061 h 062 h 063 h 064 h 065 h lcd panel display ram address segment no. *0 to *7: i ndicate corresponding display ram bits. (bits 2, 3, 6, and 7 are not used.) address com3 com2 com1 com0 n h bit3 bit2 bit1 *1 bit0 *0 segn bit7 bit6 bit5 *3 bit4 *2 segn+1 n+1h bit3 bit2 bit1 *5 bit0 *4 segn+2 bit7 bit6 bit5 *7 bit4 *6 segn+3 0: off 1: on address com3 com2 com1 com0 060h 1 1 seg0 1 0seg1 061h 1 0seg2 0 1seg3 lcd display bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1 1 0 1 1 1 1 1 0 0 0 0 1 0 1 1 1 1 1 0 1 1 0 1 1 1 1 0 1 1 1 1 0 0 1 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 0 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 example) using segments to represent "5". bit state for numerals "0" through "9"
365 14.4 operation of lcd controller/driver 14.4.2 output waveforms during lcd controller/driver operation (1/3 duty ratio) in the 1/3 duty ratio mode, the com0, com1 and com2 outputs are used by the display. com3 is not used. n output waveforms during lcd controller/driver operation (1/3 duty ratio) m 1/3 bias, 1/3 duty output waveform the maximum potential difference exists between a segment output and the corresponding common output when the segment (lcd cell) is "turned on". figure 14.4-4 "output waveforms, 1/3 bias and 1/3 duty ratio example" shows the output waveforms for the display ram contents listed in table 14.4-2 "display ram contents example". -: not used table 14.4-2 display ram contents example segment display ram contents com3 com2 com1 com0 segn - 1 0 0 segn+1 - 1 0 1
366 chapter 14 lcd controller/driver figure 14.4-4 output waveforms, 1/3 bias and 1/3 duty ratio example v 3 v 2 v 1 v 0 =v ss v 3 v 2 v 1 v 0 =v ss v 3 v 2 v 1 v 0 =v ss v 3 v 2 v 1 v 0 =v ss v 3 v 2 v 1 v 0 =v ss v 3 v 2 v 1 v 0 =v ss v 3 (on) v 2 v 1 v ss -v 1 -v 2 -v 3 (on) v 3 (on) v 2 v 1 v ss -v 1 -v 2 -v 3 (on) v 3 (on) v 2 v 1 v ss -v 1 -v 2 -v 3 (on) v 3 (on) v 2 v 1 v ss -v 1 -v 2 -v 3 (on) v 3 (on) v 2 v 1 v ss -v 1 -v 2 -v 3 (on) v 3 (on) v 2 v 1 v ss -v 1 -v 2 -v 3 (on) com0 com1 com2 com3 seg n seg n+1 difference in potential between com0 and seg n difference in potential between com1 and seg n difference in potential between com2 and seg n difference in potential between com0 and seg n+1 difference in potential between com1 and seg n+1 difference in potential between com2 and seg n+1 1 frame 1 cycle v 0 to v 3 : v0 to v3 pin voltages v 0 to v 3 : v0 to v3 pin voltage
367 14.4 operation of lcd controller/driver m lcd panel connections and display data example (1/3 duty ratio drive mode) figure 14.4-5 segment/common connections, data states and corresponding display com2 seg n+3 seg n+2 seg n * 6 * 0 * 7 * 8 * 1 * 3 * 4 * 5 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 com3 CC CC CC CC CC CC CC CC CC com2 0 1 1 0 0 1 0 1 1 com1 1 0 1 0 0 1 1 1 0 com0 1 1 1 0 0 1 0 1 1 060 h 061 h 062 h 063 h 064 h com0 com1 seg n+1 display ram segment no. lcd panel address address com3 com2 com1 com0 n h bit3 bit2 *2 bit1 *1 bit0 *0 segn bit7 bit6 *5 bit5 *4 bit4 *3 segn+1 n+1h bit3 bit2 *8 bit1 *7 bit0 *6 segn+2 0: off 1: on address com3 com2 com1 com0 060 h 001seg0 111seg1 061 h 010seg2 001seg3 062 h 111seg4 010seg5 :data in unit starting at bit 4 :data in unit starting at bit 0 lcd display bit states for numerals 0 through 9 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1 0 10 1 1 0 1 11 1 1 1 1 1 1 0 1 0 0 00 0 0 0 0 01 1 1 1 1 1 0 0 0 1 1 10 1 0 0 1 01 0 1 1 0 1 1 1 1 1 1 10 0 0 0 0 01 1 1 1 1 1 1 1 1 0 1 00 0 1 0 0 11 1 1 1 1 1 0 1 0 1 1 10 0 1 0 0 11 1 0 1 1 0 1 1 1 1 1 10 1 1 0 1 11 1 0 1 1 0 1 1 1 0 0 10 0 1 0 0 11 1 1 1 1 1 0 0 1 1 1 10 1 1 0 1 11 1 1 1 1 1 1 1 1 1 1 10 0 1 0 0 11 1 1 1 1 1 1 1 1 example) using segments to represent "5". in 1/3 duty ratio operation, to be able to define two digits in three bytes, the data stored in two bytes, with the first byte starting at bit 0, and second byte starting at bit 4. *0 to *8: indicate corresponding display ram bits. (bit3 and 7 and *2 are not used.)
368 chapter 14 lcd controller/driver 14.4.3 output waveforms during lcd controller/driver operation (1/4 duty ratio) in the 1/4 duty ratio mode, all four common outputs, com0, com1, com2, and com3 are used. n output waveforms during lcd controller/driver operation (1/4 duty ratio) m 1/3 bias, 1/4 duty output waveforms the maximum potential difference exists between a segment output and the corresponding common output when the segment (lcd cell) is "turned on". figure 14.4-6 "output waveforms, 1/3 bias and 1/4 duty ratio example" shows the output waveforms for the display ram contents listed in table 14.4-3 "display ram contents example". table 14.4-3 display ram contents example segment display ram contents com3 com2 com1 com0 segn 0100 segn+1 0101
369 14.4 operation of lcd controller/driver figure 14.4-6 output waveforms, 1/3 bias and 1/4 duty ratio example 01 v 3 v 2 v 1 v 0 =v ss v 3 v 2 v 1 v 0 =v ss v 3 v 2 v 1 v 0 =v ss v 3 v 3 v 3 v 0 =v ss v 3 v 2 v 1 v 0 =v ss v 3 v 2 v 1 v 0 =v ss v 3 (on) v 2 v 1 v ss -v 1 -v 2 -v 3 (on) v 3 (on) v 2 v 1 v ss -v 1 -v 2 -v 3 (on) v 3 (on) v 2 v 1 v ss -v 1 -v 2 -v 3 (on) v 3 (on) v 2 v 1 v ss -v 1 -v 2 -v 3 (on) v 3 (on) v 2 v 1 v ss -v 1 -v 2 -v 3 (on) v 3 (on) v 2 v 1 v ss -v 1 -v 2 -v 3 (on) com0 com1 com2 com3 seg n seg n+1 v 3 (on) v 2 v 1 v ss -v 1 -v 2 -v 3 (on) v 3 (on) v 2 v 1 v ss -v 1 -v 2 -v 3 (on) difference in potential between com0 and seg n difference in potential between com1 and seg n difference in potential between com2 and seg n difference in potential between com3 and seg n difference in potential between com0 and seg n+1 difference in potential between com1 and seg n+1 difference in potential between com2 and seg n+1 difference in potential between com3 and seg n+1 1 frame 1 cycle v 0 to v 3 : v0 to v3 pin voltages
370 chapter 14 lcd controller/driver m 8-segment lcd panel connections and display data (1/4 duty ratio drive mode) figure 14.4-7 segment/common connections, data states and corresponding display com2 seg n * 7 * 0 * 3 * 6 * 1 * 4 * 5 * 2 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 com3 1 1 1 1 0 1 1 1 com2 1 1 0 1 1 1 1 1 com1 1 0 0 0 1 1 0 1 com0 1 1 0 0 0 1 0 1 060 h 061 h 062 h 063 h com0 com1 seg n+1 com3 lcd panel display ram address segment no. *0 to *7: indicate corresponding display ram bits. address com3 com2 com1 com0 n h bit3 *3 bit2 *2 bit1 *1 bit0 *0 segn bit7 *7 bit6 *6 bit5 *5 bit4 *4 segn+1 0: off 1: on address com3 com2 com1 com0 060 h 1101seg0 0011seg1 lcd display bit states for numerals "0" through "9" bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 11011111 11001000 11110110 11111100 11101001 01111101 01111111 11011001 11111111 11111101 example) using segments to represent "5".
371 14.5 program example for lcd controller/driver 14.5 program example for lcd controller/driver this section gives a program example for lcd controller/driver. n program example for lcd controller/driver function m processing description the process writes lcd display data to display ram. the data is that required to display the numbers "0" through "9" in an lcd panel connected as shown in figure 14.4-7 "segment/ common connections, data states and corresponding display". the settings are as follows: ? internal voltage divider resistors are selected in a device with no voltage booster (lcr1: vsel = 1) ? 1/3 bias and 1/4 duty ratio are used. ? the subclock (lcr1: css = 1) is selected as the clock for frame cycle generation. ? the frame frequency is set at 32 hz (lcr1: fp1, fp0 = 11 b ) ? operation is stopped in watch mode. m coding example lcram lcr1 equ equ 0060h 0072h ;starting address of lcd display ram ; address of lcdc control register 1 (lcr1) lcdseg lcddata lcdseg cseg db db db db db db db db db db db ends 11011111b 11001000b 11110110b 11111100b 11101001b 01111101b 01111111b 11011001b 11111111b 11111101b 00000000b ; 8-segment lcd display data ; "0" ; "1" ; "2" ; "3" ; "4" ; "5" ; "6" ; "7" ; "8" ; "9" ;end ;---------- main program ----------------------------------------------------------------------------------
372 chapter 14 lcd controller/driver lcdset cseg : movw movw mov mov incw incw bnz mov : ends ep,#lcram ix,#lcddata a,@ix+00h @ep,a ep ix lcdset lcr1,#10101111b ; [code segment] ; set lcd display ram address. ; set lcd display data table address. ; continue until data end (00h) is detected. ; set lcr1 and turn lcd display on. ;--------------------------------------------------------------------------------------------------------------- end
373 chapter 15 buzzer output this chapter describes the functions and operation of the buzzer output. 15.1 "overview of buzzer output" 15.2 "block diagram of buzzer output" 15.3 "structure of buzzer output" 15.4 "buzzer register (bzcr)" 15.5 "program example for buzzer output"
374 chapter 15 buzzer output 15.1 overview of buzzer output the buzzer output can select from seven different output frequencies (square waves) and can be used for applications such as sounding a buzzer to confirm key input. the function uses the same output pin as the remote control transmit output. n buzzer output function the buzzer output function outputs a signal (square wave) suitable for applications such as sounding a buzzer to confirm an operation. ? for buzzer output, one of seven output frequencies can be selected, or the output disabled. ? four divide-by-n outputs are supplied from the timebase timer and three from the watch prescaler, for selection as the buzzer output signal. note: since divided outputs of the timebase timer and timeclock prescaler are fed as the buzzer output signal, the buzzer output will be affected when the signal source selected for it (timebase timer or watch prescaler) is cleared. check: since the timebase timer stops when the main clock oscillator stops (during subclock mode), do not select the divided output of the timebase timer as the buzzer output when subclock mode is used. check: similarly, do not select the watch prescaler as the buzzer source in a chip in which the single clock option is selected. table 15.1-1 "output frequency" lists the seven output frequencies (square waves) that can be selected for the buzzer output function. f ch : main clock oscillation frequency f cl : subclock oscillation frequency the frequencies enclosed in parentheses ( ) are for f ch = 4.2 mhz, and f cl = 32.768 khz. table 15.1-1 output frequency clock supply source buzzer output cycle square wave output (hz) timebase timer 2 12 /f ch f ch /2 12 (1.025 khz) 2 11 /f ch f ch /2 11 (2.051 khz) 2 10 /f ch f ch /2 10 (4.102 khz) 2 9 /f ch f ch /2 9 (8.203 khz) watch prescaler 2 5 /f cl f cl /2 5 (1.024 khz) 2 4 /f cl f cl /2 4 (2.048 khz) 2 3 /f cl f cl /2 3 (4.096 khz)
375 15.1 overview of buzzer output calculation example for output frequency note: for a 4.2 mhz main clock source oscillation and if the buzzer register (bzcr) selects a timebase timer divided output of f ch /2 10 (bz2, bz1, bz0 = 011b), the output frequency of the bz pin is calculated as follows: = f ch /2 10 = 4.2 mhz/1024 4.102 khz output frequency
376 chapter 15 buzzer output 15.2 block diagram of buzzer output the buzzer output consists of the following two blocks: ? buzzer output selector ? buzzer register (bzcr) n block diagram of buzzer output figure 15.2-1 block diagram of buzzer output m buzzer output selector selects one of the four frequencies output from the timebase timer or three frequencies output from the watch prescaler. m bzcr register the bzcr register to set the buzzer output frequency and enable buzzer output. buzzer output is enabled if an output frequency is specified (other than "000 b ") in the bzcr register. bz1 bz2 bz0 bzcr 2 12 /f ch 2 11 /f ch 2 10 /f ch 2 9 /f ch 2 5 /f cl 2 4 /f cl 2 3 /f cl internal data bus select buzzer output enable signal from timebase timer from watch prescaler buzzer output selector buzzer output pin f ch : main clock oscillation frequency f cl : subclock oscillation frequency p30/pwm1/bz
377 15.3 structure of buzzer output 15.3 structure of buzzer output this section describes the pin, pin block diagram, and register of the buzzer output. n buzzer output pin the buzzer output uses the p30/pwm1/bz pin. this pin can function as a cmos output port (p30), or pwm 1 output (pwm1) or the buzzer output pin (bz). n block diagram of buzzer output pin figure 15.3-1 block diagram of p30/pwm1/bz pin n buzzer output register figure 15.3-2 buzzer output register bz: this pin outputs a buzzer square wave with the specified frequency. setting a buzzer output frequency in the buzzer output register (bzcr: bz1, bz0 = other than "00b") automatically sets the p30pwm1/bz pin as the bz pin regardless of the output latch value when pwm1 is disbled. pdr (port data register) internal data bus pdr read output latch pdr write pin spl: pin state specification bit in the standby control register (stbc) n-ch p-ch stop, watch mode (spl = 1) p30/pwm1/bz pwm1 pwm1 output enable output buzzer buzzer output enable output bzcr(buzzer register) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0010 h bz2bz1bz0 -----000 b r/w r/w r/w r/w : readable and writable : unused x : indeterminate
378 chapter 15 buzzer output 15.4 buzzer register (bzcr) the buzzer register (bzcr) is used to select the buzzer output frequency and also enables buzzer output. n buzzer register (bzcr) figure 15.4-1 buzzer register (bzcr) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 0010 h bz2bz1bz0 -----000 b r/w r/w r/w bz2 bz1 bz0 buzzer selection bits 0 0 0 disables buzzer output. makes pin available for use either as a general-purpose port (p30) or pwm1 output (pwm1). 001 functions as a buzzer output pin (bz). timebase timer outputs f ch /2 12 010 f ch /2 11 011 f ch /2 10 100 f ch /2 9 101 watch prescaler outputs f cl /2 5 110 f cl /2 4 111 f cl /2 3 r/w : readable and writable : unused x : indeterminate : initial value f ch : main clock oscillation frequency f cl : subclock oscillation frequen
379 15.4 buzzer register (bzcr) table 15.4-1 buzzer register (bzcr) bits bit function bit 7 bit 6 bit 5 bit 4 unused bits ? the read value is indeterminate. ? writing to these bits has no effect on the operation. bit 2 bit 1 bit 0 bz2, bz1, bz0: buzzer selection bits ? setting "000b" disables the buzzer output and sets the pin as a general-purpose port (p30) or pwm 1 output (pwm1). ? setting other than "000b" sets the pin the as the buzzer output (bz) pin and outputs a square wave of the selected frequency. ? selects one of four divided outputs from the timebase timer or three from the timeclock prescaler. note: do not select a timebase timer division output in subclock mode. note: the subclock oscillator operates in the main-stop mode. therefore, if the pin state specification bit (stbc: spl) is "0", the buzzer output can be used even in main-stop mode by selecting one of the watch prescaler divided- by-n outputs (bz2, bz1, bz0 = 101b to 111b).
380 chapter 15 buzzer output 15.5 program example for buzzer output this section gives a program example for the buzzer output. n program example for buzzer output m processing description ? output a buzzer output of approximately 1.025 khz to the bz pin, then turn the buzzer output "off". ? for a 4.2 mhz main clock source oscillation and selecting 2 12 /f c (f c : main clock oscillation), the buzzer output frequency is as follows: m coding example buzzer output frequency = 4.2 mhz/2 12 = 4.2 mhz/4096 = 1.025 khz bzcr equ 0010h ; buzzer register ;---------- main program --------------------------------------------------------------------------------- buzon cseg : mov bzcr,#00000001b ; [code segment] ; buzzer output "on". buzoff : : : mov : ends bzcr,#00000000b ; buzzer output "off". ;----------------------------------------------------------------------------------------------------------------------------- end
381 appendix the appendices are include an i/o map and the instruction list. a "i/o map" b "instructions" c "mask options" d "programming specifications for one-time prom and eprom microcontroller" e "mb89980 series pin states"
382 appendix a i/o map appendix a i/o map table a-1 "i/o map" lists the addresses of the registers of used by the internal peripheral functions of the mb89980 series. n i/o map table a-1 i/o map address register name register description read/write initial value 00 h pdr0 port 0 data register r/w xxxxxxxx b 01 h ddr0 port 0 data direction register w 00000000 b 02 h pdr1 port 1 data register r/w xxxxxxxx b 03 h ddr1 port 1 data direction register w 00000000 b 04 h pdr2 port 2 data register r/w xxxxxxxx b 05 h ddr2 port 2 data direction register w 00000000 b 06 h (vacancy) xxxxxxxx b 07 h sycc system clock control register r/w ---mm100 b 08 h stbc standby control register r/w 00010--- b 09 h wdtc watchdog timer control register r/w 0---xxxx b 0a h tbtc timebase timer control register r/w 00---000 b 0b h wpcr watch prescaler control register r/w 00---000 b 0c h pdr3 port 3 data register r/w xxxxxxx1 b 0d h (vacancy) xxxxxxxx b 0e h pdr4 port 4 data register r/w 11111111 b 0f h pdr5 port 5 data register r/w xxxx1111 b 10 h bzcr buzzer register r/w -----000 b 11 h (vacancy) xxxxxxxx b 12 h pdr6 port 6 data register r/w xx111111 b 13 h pdr7 port 7 data register r/w xxxxxx11 b 14 h rcr1 remote control transmission register 1 r/w 00000000 b 15 h rcr2 remote control transmission register 2 r/w 0-000000 b 16 h to 17 h (vacancy) xxxxxxxx b 18 h t2cr timer 2 control register r/w x000xxx0 b
383 appendix a i/o map 19 h t1cr timer 1 control register r/w x000xxx0 b 1a h t2dr timer 2 data register r/w xxxxxxxx b 1b h t1dr timer 1 data register r/w xxxxxxxx b 1c h - 1d h (vacancy) xxxxxxxx b 1e h cntr1 pwm 1 control register r/w 0-000000 b 1f h comr1 pwm 1 compare register w xxxxxxxx b 20 h cntr2 pwm 2 control register r/w 0-000000 b 21 h comr2 pwm 2 compare register w xxxxxxxx b 22 h to 2c h (vacancy) xxxxxxxx b 2d h adc1 a/d control register 1 r/w 00000000 b 2e h adc2 a/d control register 2 r/w ---00001 b 2f h adcd a/d data register r/w xxxxxxxx b 30 h eie1 external interrupt 1 control register r/w 00000000 b 31 h eif1 external interrupt 1 flag register r/w ----0000 b 32 h eie2 external interrupt 2 control register r/w 00000000 b 33 h eif2 external interrupt 2 flag register r/w -------0 b 34 h to 3f h (vacancy) xxxxxxxx b 40 h purr0 pull-up control register 0 (for mb89p985/pv980 only) r/w 11111111 b 41 h purr1 pull-up control register 1 (for mb89p985/pv980 only) r/w 11111111 b 42 h purr5 pull-up control register 5 (for mb89p985/pv980 only) r/w ----1111 b 43 h to 5f h (vacancy) xxxxxxxx b 60 h to 66 h vram display ram r/w xxxxxxxx b 67 h to 71 h (vacancy) xxxxxxxx b 72 h lcr1 lcd control register 1 r/w 00010000 b 73 h lcr2 lcd control register 2 (for mb89p985/pv980 only) r/w 0--0000- b 74 h to 7b h (vacancy) xxxxxxxx b 7c h ilr1 interrupt level setting register 1 w 11111111 b 7d h ilr2 interrupt level setting register 2 w 11111111 b 7e h ilr3 interrupt level setting register 3 w 11111111 b table a-1 i/o map address register name register description read/write initial value
384 appendix a i/o map m read/write access symbols r/w: readable and writable r: read-only w: write-only m initial value symbols 0: the initial value of this bit is "0". 1: the initial value of this bit is "1". x: the initial value of this bit is undefined. m: the initial value of this bit is determined by mask option. check: do not use vacancies. 7f h itr interrupt test register access prohibited xxxxxx00 b table a-1 i/o map address register name register description read/write initial value
385 appendix b instructions appendix b instructions this appendix describes the f 2 mc-8l instruction set. b.1 "instruction list symbols" b.2 "addressing" b.3 "special instructions" b.4 "f 2 mc-8l instructions" b.5 "instruction map" b.6 "bit manipulation instructions (setb, clrb)"
386 appendix b instructions b.1 instruction list symbols table b.1-1 "instruction list symbols"lists the meaning of the symbols and table b.1-2 "instruction list columns"lists the meaning of the columns used in section b.4 "f 2 mc-8l instruction list". n instruction list symbols table b.1-1 instruction list symbols symbol meaning dir direct address (8 bits) off offset (8 bits) ext extended address (16 bits) #vct vector table number (3 bits) #d8 immediate data (8 bits) #d16 immediate data (16 bits) dir: b bit direct address (8:3 bits) rel branch relative address (8 bits) @ register indirect (example: @a, @ix, @ep) a accumulator a (whether its length is 8 or 16 bits is determined by the instruction in use.) ah upper 8 bits of the accumulator a (8 bits) al lower 8 bits of the accumulator a (8 bits) t temporary accumulator t (whether its length is 8 or 16 bits is determined by the instruction in use.) th upper 8 bits of the temporary accumulator t (8 bits) tl lower 8 bits of the temporary accumulator t (8 bits) ix index register ix (16 bits) ep extra pointer ep (16 bits) pc program counter pc (16 bits) sp stack pointer sp (16 bits) ps program status ps (16 bits) dr accumulator a or index register ix (16 bits) ccr condition code register ccr (8 bits)
387 appendix b instructions rp register bank pointer rp (5 bits) ri general-purpose register ri (8 bits, i = 0 to 7) indicates that the very is the immediate data. (whether its length is 8 or 16 bits is determined by the instruction in use.) () indicates that the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.) (()) the address indicated by the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.) table b.1-2 instruction list columns column description mnemonic assembler notation of an instruction ~ number of instructions # number of bytes operation operation of an instruction tl, th, ah a content change when each of the tl, th, and ah instructions is executed. symbols in the column indicate the following: ? "-" indicate no change. ? dh is the 8 upper bits of operation description data. ? al and ah must become the contents of al and ah immediately before the instruction is executed. ? 00 becomes 00. n, z, v, c an instruction of which the corresponding flag will change. if + is written in this column, the relevant instruction will change its corresponding flag. op code code of an instruction. if an instruction is more than one code, it is written according to the following rule: example: "48 to 4f" <-- this indicates 48, 49 ... 4f. table b.1-1 instruction list symbols symbol meaning
388 appendix b instructions b.2 addressing the f 2 mc-8l supports the following ten addressing modes: ? direct addressing ? extended addressing ? bit direct addressing ? index addressing ? pointer addressing ? general-purpose register addressing ? immediate addressing ? vector addressing ? relative addressing ? inherent addressing n addressing modes m direct addressing indicated by "dir" in the instruction list. used to access the area between "0000h" and "00ffh". for direct addressing, the upper one byte of the address is "00h" and the operand specifies the lower one byte. figure b.2-1 "direct addressing" shows an example. figure b.2-1 direct addressing m extended addressing indicated by "ext" in the instruction list. used to access the entire 64-kbyte area. for extended addressing, the first operand specifies the upper one byte of the address and the second operand specifies the lower one byte. figure b.2-2 "extended addressing" shows an example. figure b.2-2 extended addressing mov 1 2h , a 0 0 1 2 h 4 5 h a 4 5 h 5 6 h 7 8 h a 5 6 7 8 h 1 2 3 4 h 1 2 3 5 h movw a, 1 2 3 4h
389 appendix b instructions m bit direct addressing indicated by "dir: b" in the instruction list. used to access the area between "0000h" and "00ffh" in bit units. for bit direct addressing, the upper one byte of the address is "00h" the operand specifies the lower one byte of the address, and the lower three bits of the operation code specify the bit position. figure b.2-3 "bit direct addressing" shows an example. figure b.2-3 bit direct addressing m index addressing indicated by "@ix+off" in the instruction list. used to access the entire 64-kbyte area. index addressing generates the address is obtained by adding the sign-extended contents of the first operand to the index register (ix). figure b.2-4 "index addressing" shows an example. figure b.2-4 index addressing m pointer addressing indicated by "@ep" in the instruction list. used to access the entire 64-kbyte area. pointer addressing uses the extra pointer (ep) the address. figure b.2-5 "pointer addressing" shows an example. figure b.2-5 pointer addressing m general-purpose register addressing indicated by "ri" in the instruction list. used to access the general-purpose register area register bank. for general-purpose register addressing, the upper one byte of the address is fixed at "01" and the lower byte is generated from the register bank pointer (rp) and the lower three bits of the operation code. the cpu accesses the resulting address. figure b.2-6 "general-purpose register addressing" shows an example. figure b.2-6 general-purpose register addressing setb 3 : 2 0034 h xxxxx1xx b 76543210 4h 1 2 h 3 4 h a 1 2 3 4 h 2 7 f f h 2 8 0 0 h movw a, @ix+5 ah ix 2 7 a 5 h + 1 2 h 3 4 h a 1 2 3 4 h 2 7 a 5 h 2 7 a 6 h movw a, @ep ep 2 7 a 5 h a b h a a b h 0 1 5 6 h mov a, r6 rp 0 1 0 1 0 b +
390 appendix b instructions m immediate addressing indicated by "#d8" in the instruction list. used when immediate data is required. in immediate addressing, the operand is used directly as immediate data. the operation code determines whether the data is byte or word. figure b.2-7 "immediate addressing" shows an example. figure b.2-7 immediate addressing m vector addressing indicated by "vct" in the instruction list. used to branch to a subroutine address stored in the vector table. for vector addressing, the "vct" data is contained in the operation code. table b.2-1 "vector table address corresponding to "vct""lists the correspondence between "vct" and the resulting address. figure b.2-8 "vector addressing" shows an example. figure b.2-8 vector addressing m relative addressing indicated by "rel" in the instruction list. used to branch to a destination in the area 128 bytes above or below the program counter (pc). relative addressing adds the sign-extended contents of the first operand to the pc and stores the result in the pc. figure b.2-9 "relative addressing" shows an example. mov a, #5 6h a h 6 5 table b.2-1 vector table address corresponding to "vct" #vct vector table address (branch destination upper address: lower address) 0 ffc0 h : ffc1 h 1 ffc2 h : ffc3 h 2 ffc4 h : ffc5 h 3 ffc6 h : ffc7 h 4 ffc8 h : ffc9 h 5ffca h : ffcb h 6 ffcc h : ffcd h 7 ffce h : ffcf h f e h d c h pc f e d c h f f c a h f f c b h callv #5 (conversion)
391 appendix b instructions figure b.2-9 relative addressing this example branches to the address containing the bne operation code and therefore results in an endless loop. m inherent addressing inherent addressing is used for instructions in the instruction list that do not have operands and for which the operation code determines the operation. the operation of inherent addressing depends on the instruction. figure b.2-10 "inherent addressing" shows an example. figure b.2-10 inherent addressing old pc bne f eh 9abc h + fffe h new pc + 9 a b c h 9 a b a h old pc new pc 9 a b c h 9 a h nop b d
392 appendix b instructions b.3 special instructions this section describes special instructions, other than addressing. n special instructions m jmp @a this instruction moves the address contained in the accumulator (a) to the program counter (pc) and branches to the new address. this instruction can be used to perform an n option branch by placing n branch destination addresses in a table and moving the desired address to the accumulator. figure b.3-1 "jmp @a" shows an outline of the instruction operation. figure b.3-1 jmp @a m movw a,pc this instruction stores the pc contents in the accumulator a. this performs the opposite operation to "jmp @a". by executing this instruction in the main routine and calling a particular subroutine, the subroutine can determine whether the contents of a match a predetermined value. the subroutine can check whether program runaway has occurred by checking whether or not execution has branched from an expected location. figure b.3-2 "movw a,pc" shows an outline of the instruction operation. figure b.3-2 movw a,pc the content of a after executing this instruction is the address of the next instruction (not the address containing the operation code of this instruction. accordingly, the value "1234 h " stored in a in the example shown in figure b.3-2 "movw a,pc" is the address of the next operation code after "movw a, pc". (before execution) (after execution) a 1 2 3 4 h old pc x x x x h a1 2 3 4 h new pc 1 2 3 4 h (before execution) (after execution) a x x x x h old pc 1 2 3 3 h a1 2 3 4 h new pc 1 2 3 4 h
393 appendix b instructions m mulu a this instruction performs an unsigned multiplication of al (lower 8 bits of the accumulator) and tl (lower 8 bits of the temporary accumulator) and stores the 16-bit result in a. the contents of t (temporary accumulator) does not change. the arithmetic operation does not use the pre- execution contents of ah (upper 8 bits of the accumulator) and th (upper 8 bits of the temporary accumulator). since the flags remain unchanged, use care when branching is required based on the result of multiplication. figure b.3-3 "mulu a" shows an outline of the instruction operation. figure b.3-3 mulu a m divu a this instruction divides the 16 bits of t by the 8 bits of al, treating the data as unsigned. the instruction stores the result in al and the remainder in tl, both as 8 bit data. ah and th are both set to "zero". the arithmetic operation does not use the value of ah prior to instruction execution. the result is not assured for data that produces a result that exceeds 8 bits. as there is no indication that the result exceeded 8 bits, check the data before performing. since the flags remain unchanged, use care when branching is required based on the result of the division. figure b.3-4 "divu a" shows an outline of the instruction operation. figure b.3-4 divu a m xchw a,pc this instruction exchanges the contents of a and pc, and as a result branches to the address corresponding to contents of a before execution. the contents of a after execution assume the address next to the address where the operation code of the "xchw a,pc" is stored. the instruction can be used to specify a table in the main routine which is used in a subroutine. figure b.3-5 "xchw a,pc" shows an outline of the instruction operation. figure b.3-5 xchw a,pc (before execution) (after execution) a 5 6 7 8 h t 1 2 3 4 h a1 8 6 h t 1 2 3 4 h 0 (before execution) (after execution) a5 6 7 8 h t 1 8 6 2 h a0 0 3 4 h t 0 0 0 2 h (before execution) (after execution) a5 6 7 8 h pc 1 2 3 4 h a1 2 3 5 h pc 5 6 7 8 h
394 appendix b instructions the content of a after executing this instruction is the address of the next instruction (not the address containing the operation code of this instruction). accordingly, the value "1235 h " stored in a in the example shown in figure b.3-5 "xchw a,pc" is the address of the next operation code after "xchw a,pc". therefore, the value of a is "1235 h " not "1234 h ". figure b.3-6 "example using xchw a, pc" shows an assembly language example. figure b.3-6 example using xchw a, pc m callv #vct this instruction is used to branch to a subroutine address in the vector table. the instruction saves the return address (contents of the pc) to the address corresponding to the sp (stack pointer) branches to the address stored in the vector table using vector addressing. as "callv #vct" is a single-byte instruction, using this instruction for commonly used subroutines reduces the overall program size. figure b.3-7 "execution example of callv #3" shows an outline of the instruction operation. figure b.3-7 execution example of callv #3 the content of pc saved to stack area after executing this instruction is the address of next instruction (not the address containing the operation code of this instruction). accordingly, the value "5679 h " saved to stack (1232 h , 1233 h ) in the example shown in figure b.3-7 "execution example of callv #3" is the address (return address) of the next operation code after "movw a,pc". (main routine) (subroutine) ? ? ? movw a, #putsub putsub xchw a, ep xchw a, pc pushw a db 'put out data',eol pts1 mov a, @ep movw a, 1234 h incw ep ? mov io, a ?cmp a, #eol ?bne pts1 popw a xchw a, ep jmp @a table d ata output here (before execution) (after execution) pc sp 5 6 7 8 h 1 2 3 4 h pc sp f e d c h 1 2 3 2 h x x h x x h f e h d c h 1 2 3 2 h 1 2 3 3 h f f c 6 h f f c 7 h 5 6 h 7 9 h f e h d c h 1 2 3 2 h 1 2 3 3 h f f c 6 h f f c h (-2) 7
395 appendix b instructions b.4 f 2 mc-8l instructions table b.4-1 "transfer instructions"to b.4-4 "other instructions"list the f 2 mc-8l instructions. n transfer instructions table b.4-1 transfer instructions no. mnemonic ~ # operation tl th ah nzvc op code 1 2 3 4 5 mov dir, a mov @ix+off, a mov ext, a mov @ep, a mov ri, a 3 4 4 3 3 2 2 3 1 1 (dir) <-- (a) ((ix)+off) <-- (a) (ext) <-- (a) ((ep)) <-- (a) (ri) <-- (a) - - - - - - - - - - - - - - - ---- ---- ---- ---- ---- 45 46 61 47 48 to 4f 6 7 8 9 10 mov a, #d8 mov a, dir mov a, @ix+off mov a, ext mov a, @a 2 3 4 4 3 2 2 2 3 1 (a) <-- d8 (a) <-- (dir) (a) <-- ((ix)+off) (a) <-- (ext) (a) <-- ((a)) al al al al al - - - - - - - - - - ++-- ++-- ++-- ++-- ++-- 04 05 06 60 92 11 12 13 14 15 mov a, @ep mov a, ri mov dir, #d8 mov @ix+off, #d8 mov @ep, #d8 3 3 4 5 4 1 1 3 3 2 (a) <-- ((ep)) (a) <-- (ri) (dir) <-- d8 ((ix)+off) <-- d8 ((ep)) <-- d8 al al - - - - - - - - - - - - - ++-- ++-- ---- ---- ---- 07 08 to 0f 85 86 87 16 17 18 19 20 mov ri, #d8 movw dir, a movw @ix+off, a movw ext, a movw @ep, a 4 4 5 5 4 2 2 2 3 1 (ri) <-- d8 (dir) <-- (ah), (dir+1) <-- (al) ((ix)+off) <-- (ah), ((ix)+off+1) <-- (al) (ext) <-- (ah), (ext+1) <-- (al) ((ep)) <-- (ah), ((ep)+1) <-- (al) - - - - - - - - - - - - - - - ---- ---- ---- ---- ---- 88 to 8f d5 d6 d4 d7 21 22 23 24 25 movw ep, a movw a, #d16 movw a, dir movw a, @ix+off movw a, ext 2 3 4 5 5 1 3 2 2 3 (ep) <-- (a) (a) <-- d16 (ah) <-- (dir), (al) <-- (dir+1) (ah) <-- ((ix)+off), (al) <-- ((ix)+off+1) (ah) <-- (ext), (al) <-- (ext+1) - al al al al - ah ah ah ah - dh dh dh dh ---- ++-- ++-- ++-- ++-- e3 e4 c5 c6 c4 26 27 28 29 30 movw a, @a movw a, @ep movw a, ep movw ep, #d16 movw ix, a 4 4 2 3 2 1 1 1 3 1 (ah) <-- ((a)), (al) <-- ((a)+1) (ah) <-- ((ep)), (al) <-- ((ep)+1) (a) <-- (ep) (ep) <-- d16 (ix) <-- (a) al al - - - ah ah - - - dh dh dh - - ++-- ++-- ---- ---- ---- 93 c7 f3 e7 e2
396 appendix b instructions check: the automatic transfer to the t register is tl <-- al for instructions that perform a byte transfer to a. operands in more than one operand instruction must be stored in the order in which their mnemonics are written. n arithmetic operation instructions 31 32 33 34 35 movw a, ix movw sp, a movw a, sp mov @a, t movw @a, t 2 2 2 3 4 1 1 1 1 1 (a) <-- (ix) (sp) <-- (a) (a) <-- (sp) ((a)) <-- (t) ((a)) <-- (th), ((a)+1) <-- (tl) - - - - - - - - - - dh - dh - - ---- ---- ---- ---- ---- f2 e1 f1 82 83 36 37 38 39 40 movw ix, #d16 movw a, ps movw ps, a movw sp, #d16 swap 3 2 2 3 2 3 1 1 3 1 (ix) <-- d16 (a) <-- (ps) (ps) <-- (a) (sp)<-- d16 (ah) <-- --> (al) - - - - - - - - - - - dh - - al ---- ---- ++++ ---- ---- e6 70 71 e5 10 41 42 43 44 45 setb dir:b clrb dir:b xch a, t xchw a, t xchw a, ep 4 4 2 3 3 2 2 1 1 1 (dir):b <-- 1 (dir):b <-- 0 (al) <-- --> (tl) (a) <-- --> (t) (a) <-- --> (ep) - - al al - - - - ah - - - - dh dh ---- ---- ---- ---- ---- a8 to af a0 to a7 42 43 f7 46 47 48 xchw a, ix xchw a, sp movw a, pc 3 3 2 1 1 1 (a) <-- --> (ix) (a) <-- --> (sp) (a) <-- (pc) - - - - - - dh dh dh ---- ---- ---- f6 f5 f0 table b.4-1 transfer instructions no. mnemonic ~ # operation tl th ah nzvc op code table b.4-2 arithmetic opeation instructions no. mnemonic ~ # operation tl th ah nzvc op code 1 2 3 4 5 addc a, ri addc a, #d8 addc a, dir addc a, @ix+off addc a, @ep 3 2 3 4 3 1 2 2 2 1 (a) <-- (a)+(ri)+c (a) <-- (a)+d8+c (a) <-- (a)+(dir)+c (a) <-- (a)+((ix)+off)+c (a) <-- (a)+((ep))+c - - - - - - - - - - - - - - - ++++ ++++ ++++ ++++ ++++ 28 to 2f 24 25 26 27 6 7 8 9 10 addcw a addc a subc a, ri subc a, #d8 subc a, dir 3 2 3 2 3 1 1 1 2 2 (a) <-- (a)+(t)+c (al) <-- (al)+(tl)+c (a) <-- (a)-(ri)-c (a) <-- (a)-d8-c (a) <-- (a)-(dir)-c - - - - - - - - - - dh - - - - ++++ ++++ ++++ ++++ ++++ 23 22 38 to 3f 34 35 11 12 13 14 15 subc a, @ix+off subc a, @ep subcw a subc a inc ri 4 3 3 2 4 2 1 1 1 1 (a) <-- (a)-((ix)+off)-c (a) <-- (a)-((ep))-c (a) <-- (t)-(a)-c (al) <-- (tl)-(al)-c (ri) <-- (ri)+1 - - - - - - - - - - - - dh - - ++++ ++++ ++++ ++++ +++- 36 37 33 32 c8 to cf
397 appendix b instructions 16 17 18 19 20 incw ep incw ix incw a dec ri decw ep 3 3 3 4 3 1 1 1 1 1 (ep) <-- (ep)+1 (ix) <-- (ix)+1 (a) <-- (a)+1 (ri) <-- (ri)-1 (ep) <-- (ep)-1 - - - - - - - - - - - - dh - - ---- ---- ++-- +++- ---- c3 c2 c0 d8 to df d3 21 22 23 24 25 decw ix decw a mulu a divu a andw a 3 3 19 21 3 1 1 1 1 1 (ix) <-- (ix)-1 (a) <-- (a)-1 (a) <-- (al)*(tl) (a) <-- (t)/(al), mod --> (t) (a) <-- (a) ^ (t) - - - dl - - - - 00 - - dh dh 00 dh ---- ++-- ---- ---- ++r- d2 d0 01 11 63 26 27 28 29 30 orw a xorw a cmp a cmpw a rorc a 3 3 2 3 2 1 1 1 1 1 (a) <-- (a) v (t) (a) <-- (a) " (t) (tl)-(al) (t)-(a) - - - - - - - - - - dh dh - - - ++r- ++r- ++++ ++++ ++-+ 73 53 12 13 03 31 32 33 34 35 rolc a cmp a, #d8 cmp a, dir cmp a, @ep cmp a, @ix+off 2 2 3 3 4 1 2 2 1 2 (a)-d8 (a)-(dir) (a)-((ep)) (a)-((ix)+off) - - - - - - - - - - - - - - - ++-+ ++++ ++++ ++++ ++++ 02 14 15 17 16 36 37 38 39 40 cmp a, ri daa das xor a xor a, #d8 3 2 2 2 2 1 1 1 1 2 (a)-(ri) decimal adjust for addition decimal adjust for subtraction (a) <-- (al) " (tl) (a) <-- (al) " d8 - - - - - - - - - - - - - - - ++++ ++++ ++++ ++r- ++r- 18 to 1f 84 94 52 54 41 42 43 44 45 xor a, dir xor a, @ep xor a, @ix+off xor a, ri and a 3 3 4 3 2 2 1 2 1 1 (a) <-- (al) " (dir) (a) <-- (al) " ((ep)) (a) <-- (al) " ((ix)+off) (a) <-- (al) " (ri) (a) <-- (al) ^ (tl) - - - - - - - - - - - - - - - ++r- ++r- ++r- ++r- ++r- 55 57 56 58 to 5f 62 46 47 48 49 50 and a, #d8 and a, dir and a, @ep and a, @ix+off and a, ri 2 3 3 4 3 2 2 1 2 1 (a) <-- (al) ^ d8 (a) <-- (al) ^ (dir) (a) <-- (al) ^ ((ep)) (a) <-- (al) ^ ((ix)+off) (a) <-- (al) ^ (ri) - - - - - - - - - - - - - - - ++r- ++r- ++r- ++r- ++r- 64 65 67 66 68 to 6f 51 52 53 54 55 or a or a, #d8 or a, dir or a, @ep or a, @ix+off 2 2 3 3 4 1 2 2 1 2 (a) <-- (al) v (tl) (a) <-- (al) v d8 (a) <-- (al) v (dir) (a) <-- (al) v ((ep)) (a) <-- (al) v ((ix)+off) - - - - - - - - - - - - - - - ++r- ++r- ++r- ++r- ++r- 72 74 75 77 76 table b.4-2 arithmetic opeation instructions no. mnemonic ~ # operation tl th ah nzvc op code c a c a
398 appendix b instructions n branch instructions 56 57 58 59 60 or a, ri cmp dir, #d8 cmp @ep, #d8 cmp @ix+off, #d8 cmp ri, #d8 3 5 4 5 4 1 3 2 3 2 (a) <-- (al) v (ri) (dir)-d8 ((ep))-d8 ((ix)+off)-d8 (ri)-d8 - - - - - - - - - - - - - - - ++r- ++++ ++++ ++++ ++++ 78 to 7f 95 97 96 98 to 9f 61 62 incw sp decw sp 3 3 1 1 (sp) <-- (sp)+1 (sp) <-- (sp)-1 - - - - - - ---- ---- c1 d1 table b.4-2 arithmetic opeation instructions no. mnemonic ~ # operation tl th ah nzvc op code table b.4-3 branch instructions no. mnemonic ~ # operation tl th ah nzvc op code 1 2 3 4 5 bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel 3 3 3 3 3 2 2 2 2 2 if z=1 then pc <-- pc+rel if z=0 then pc <-- pc+rel if c=1 then pc <-- pc+rel if c=0 then pc <-- pc+rel if n=1 then pc <-- pc+rel - - - - - - - - - - - - - - - ---- ---- ---- ---- ---- fd fc f9 f8 fb 6 7 8 9 10 bp rel blt rel bge rel bbc dir:b, rel bbs dir:b, rel 3 3 3 5 5 2 2 2 3 3 if n=0 then pc <-- pc+rel if v " n=1 then pc <-- pc+rel if v " n=0 then pc <-- pc+rel if (dir:b)=0 then pc <-- pc+rel if (dir:b)=1 then pc <-- pc+rel - - - - - - - - - - - - - - - ---- ---- ---- -+-- -+-- fa ff fe b0 to b7 b8 to bf 11 12 13 14 15 jmp @a jmp ext callv #vct call ext xchw a, pc 2 3 6 6 3 1 3 1 3 1 (pc) <-- (a) (pc) <-- ext vector call subroutine call (pc) <-- (a), (a) <-- (pc)+1 - - - - - - - - - - - - - - dh ---- ---- ---- ---- ---- e0 21 e8 to ef 31 f4 16 17 ret reti 4 6 1 1 return from subroutine return form interrupt - - - - - - ---- restore 20 30
399 appendix b instructions n other instructions table b.4-4 other instructions no. mnemonic ~ # operation tl th ah nzvc op code 1 2 3 4 5 pushw a popw a pushw ix popw ix nop 4 4 4 4 1 1 1 1 1 1 - - - - - - - - - - - dh - - - ---- ---- ---- ---- ---- 40 50 41 51 00 6 7 8 9 clrc setc clri seti 1 1 1 1 1 1 1 1 - - - - - - - - - - - - ---r ---s ---- ---- 81 91 80 90
400 appendix b instructions b.5 instruction map table b.5-1 "f 2 mc-8l instruction map" lists the f 2 mc-8l instruction map. n instruction map table b.5-1 f 2 mc-8l instruction map h l 0123456789abcdef 0 nop swap ret reti pushw popw mov movw clri seti clrb bbc incw decw jmp movw a a a,ext a,ps dir:0 dir:0,rel a a @a a,pc 1 mulu divu jmp call pushw popw mov movw clrc setc clrb bbc incw decw movw movw a a addr16 addr16 ix ix ext,a ps,a dir:1 dir:1,rel sp sp sp,a a,sp 2 rolc cmp addc subc xch xor and or mov mov clrb bbc incw decw movw movw aaaaa,taaa@a,ta,@adir:2dir:2,relixixix,aa,ix 3 rorc cmpw addcw subcw xchw xorw andw orw movw movw clrb bbc incw decw movw movw aaaaa,taaa @a,ta,@adir:3dir:3,relepepep,aa,ep 4 mov cmp addc subc xor and or daa das clrb bbc movw movw movw xchw a,#d8 a,#d8 a,#d8 a,#d8 a,#d8 a,#d8 a,#d8 dir:4 dir:4,rel a,ext ext,a a,#d16 a,pc 5 mov cmp addc subc mov xor and or mov cmp clrb bbc movw movw movw xchw a,dir a,dir a,dir a,dir dir,a a,dir a,dir a,dir dir,#d8 dir,#d8 dir:5 dir:5,rel a,dir dir,a sp,#d16 a,sp 6 mov cmp addc subc mov xor and or mov cmp clrb bbc movw movw movw xchw a,@ix+d a,@ix+d a,@ix+d a,@ix+d @ix+d,a a,@ix+d a,@ix+d a,@ix+d @ix+d,#d8 @ix+d,#d8 dir:6 dir:6,rel a,@ix+d @ix+d,a ix,#d16 a,ix 7 mov cmp addc subc mov xor and or mov cmp clrb bbc movw movw movw xchw a,@ep a,@ep a,@ep a,@ep @ep, a a,@ep a,@ep a,@ep @ep, #d8 @ep, #d8 dir:7 dir:7,rel a,@ep @ep,a ep ,#d16 a,ep 8 mov cmp addc subc mov xor and or mov cmp setb bbs inc dec callv bnc a,r0 a,r0 a,r0 a,r0 r0,a a,r0 a,r0 a,r0 r0,#d8 r0,#d8 dir:0 dir:0,rel r0 r0 #0 rel 9 mov cmp addc subc mov xor and or mov cmp setb bbs inc dec callv bc a,r1 a,r1 a,r1 a,r1 r1,a a,r1 a,r1 a,r1 r1,#d8 r1,#d8 dir:1 dir:1,rel r1 r1 #1 rel a mov cmp addc subc mov xor and or mov cmp setb bbs inc dec callv bp a,r2 a,r2 a,r2 a,r2 r2,a a,r2 a,r2 a,r2 r2,#d8 r2,#d8 dir:2 dir:2,rel r2 r2 #2 rel b mov cmp addc subc mov xor and or mov cmp setb bbs inc dec callv bn a,r3 a,r3 a,r3 a,r3 r3,a a,r3 a,r3 a,r3 r3,#d8 r3,#d8 dir:3 dir:3,rel r3 r3 #3 rel c mov cmp addc subc mov xor and or mov cmp setb bbs inc dec callv bnz a,r4 a,r4 a,r4 a,r4 r4,a a,r4 a,r4 a,r4 r4,#d8 r4,#d8 dir:4 dir:4,rel r4 r4 #4 rel d mov cmp addc subc mov xor and or mov cmp setb bbs inc dec callv bz a,r5 a,r5 a,r5 a,r5 r5,a a,r5 a,r5 a,r5 r5,#d8 r5,#d8 dir:5 dir:5,rel r5 r5 #5 rel e mov cmp addc subc mov xor and or mov cmp setb bbs inc dec callv bge a,r6 a,r6 a,r6 a,r6 r6,a a,r6 a,r6 a,r6 r6,#d8 r6,#d8 dir:6 dir:6,rel r6 r6 #6 rel f mov cmp addc subc mov xor and or mov cmp setb bbs l inc dec callv blt a,r7 a,r7 a,r7 a,r7 r7,a a,r7 a,r7 a,r7 r7,#d8 r7,#d8 dir:7 dir:7,rel r7 r7 #7 rel
401 appendix b instructions b.6 bit manipulation instructions (setb, clrb) the bit manipulation instructions use a different read operation to the normal operation for some bits of peripheral function registers. n read-modify-write operation bit manipulation instructions set to "1" (setb) or clear to "0" (clrb) the specified bit only of a register or ram location. however, as the cpu handles data in 8-bit units, the actual operation consists of reading the 8-bit data, modifying the specified bit, then writing the result back to the same address. this is called a read-modify-write operation. table b.6-1 "bus operation for bit manipulation instructions" shows the bus operation for bit manipulation instructions. n read source when executing bit manipulation instructions the read source for a read-modify-write of some i/o ports and interrupt request flag bits is different than for a standard read. m i/o ports (bit manipulation instructions) for some i/o ports, a standard read reads the i/o pin values whereas a bit manipulation instruction reads, the output latch value. this is to prevent unintentionally modifying other output latch bit values and is independent of the pin input/output direction or pin state. m interrupt request flag bits (bit manipulation instructions) for interrupt request flag bits, a standard read reads the flag bit to determine whether an interrupt has occurred. bit manipulation instructions, however, always read interrupt request flag bits as "1". this is to prevent unintentionally clearing the flag by writing "0" to the interrupt request flag bit when performing bit manipulation of a different bit. table b.6-1 bus operation for bit manipulation instructions code mnemonic ~ cycle address bus data bus rd wr rmw a0 to a7 a8 to af clrb dir:b setb dir:b 41 2 3 4 n+1 dir address dir address n+2 dir data data next instruction 0 0 1 0 1 1 0 1 0 1 0 0
402 appendix c mask options appendix cmask options this appendix lists the mask options for the mb89980 series. n mask options table c-1 mask options no. part number mb89983 mb89p985 mb89pv980 specifying procedure specify when ordering masking setting with software setting with software 1 pull-up resistors p00 to p07, p10 to p17, p20 to p27, p40 to p47, p50 to p53, p60 to p65 selectable per pin. pull-ups for pins p40 to p47 and p60 to p65 can only be specified, however, when the lcd segment output option is not selected. also, p50 to p53 must be set to without a pull- up resistor when an a/ d converter is used. selectable per pin by pull-up control registers. pull-up resistors are not available for p20 to p27, p40 to p47 and p60 to p65. furthermore, p50 to p53 must be set to without a pull-up resistor when an a/d converter is used. selectable per pin by pull-up control registers. pull-up resistors are not available for p20 to p27, p40 to p47 and p60 to p65. furthermore, p50 to p53 must be set to without a pull-up resistor when an a/d converter is used. 2 power-on reset ? with power-on reset ? without power-on reset selectable fixed with power-on reset fixed with power-on reset 3 main clock oscillation stabilization delay time initial value* selection (f ch = 4.2 mhz) ?00: 2 4 /f ch (approx. 0 ms) ?01: 2 12 /f ch (approx. 1.0 ms) ?10: 2 16 /f ch (approx. 15.6 ms) ?11: 2 18 /f ch (approx. 62.4 ms) selectable fixed to oscillation stabilization time of 2 18 /f ch (approx. 62.4 ms). fixed to oscillation stabilization time of 2 18 /f ch (approx. 62.4 ms). 4 main clock frequency determining device: ? crystal/ceramic resonator ?cr selectable crystal or ceramic resonator only crystal or ceramic resonator only 5 reset pin output ? with reset output ? without reset output selectable fixed with reset output fixed with reset output
403 appendix c mask options 6 clock mode selection ? dual-clock mode ? single-clock mode selectable selection by version number 101 : single clock 201 : dual clock selection by version number 101 : single clock 201 : dual clock table c-1 mask options no. part number mb89983 mb89p985 mb89pv980 specifying procedure specify when ordering masking setting with software setting with software f ch : main clock source oscillation frequency *: this option selects the state to which the oscillator stabilization "wait time" bits of the system control register (sycc: wt1, wt0) are initialized at reset. table c-2 mask options (segment options) port pin names corresponding to lcd controller-driver common and segment outputs part number mb89983 p40 to p43 p44 to p47 p60 to p61 p62 to p65 p70 p71 specifying procedure specify when ordering masking oooooseg0 to seg13 (14 pins) com0 to com3 (4 pins) specify as seg=3 x o o o o seg4 to seg13 (10 pins) com0 to com3 (4 pins) specify as seg=2 x x o o o seg8 to seg13 (6 pins) com0 to com3 (4 pins) specify as seg=1 xxxxxno segment output com0, com1 (2 pins) specify as seg=0 o: used as common/segment output pins. (pull-up resistors may not be selected for these pins.) x: used as output-only port pins. (except for pins p70 and p71, pull-up resistors may be selected.) table c-3 version number version features mass production product one-time prom product piggyback product clock mode mb89983 mb89p985-101 mb89pv980-101 single clock mb89983 mb89p985-201 mb89pv980-201 dual clock
404 appendix c mask options table c-4 ordering information part number package remarks mb89983-xxx-pfv 64-pin plastic lqfp (fpt-64p-m03) mb89983-xxx-pfm 64-pin plastic qfp (fpt-64p-m09) mb89p985pfv-101 64-pin plastic lqfp (fpt-64p-m03) single clock mb89p985pfm-101 64-pin plastic qfp (fpt-64p-m09) mb89p985pfv-201 64-pin plastic lqfp (fpt-64p-m03) dual clock mb89p985pfm-201 64-pin plastic qfp (fpt-64p-m09) mb89pv980-101 64-pin ceramic mqfp (mqp-64c-p01) single clock mb89pv980-201 64-pin ceramic mqfp (mqp-64c-p01) dual clock
405 appendix d programming specifications for one-time prom and eprom microcontrollers appendix d programming specifications for one-time prom and eprom microcontrollers in eprom mode, the mb89p985 function equivalent to the mbm27c256a. this allows the prom to be programmed with a general-purpose eprom programmer by using the dedicated adaptor. note that the electronic signature mode cannot be used. d.1 programming to the one-time prom microcontroller d.2 programming yield and erasure d.3 programming to the eprom with piggyback/evaluation device
406 appendix d programming specifications for one-time prom and eprom microcontrollers d.1 programming to the one-time prom microcontroller n eprom programmer socket adaptor connect the jumper pin on the adapter to vss. depending on the eprom programmer, inserting a capacitor of about 0.1 f between vpp and vss or vcc and vss can stabilize programming operations. table d.1-1 "eprom programmer socket adaptor" lists the eprom programmer socket adaptors. inquiry : sun hayato co., ltd.: tel. 81-3-3802-5760 n memory map in eprom mode figure d.1-1 memory map in eprom mode" shows the memory map in eprom mode. write the option data in the option setting area after consulting the "otprom option bit map". figure d.1-1 memory map in eprom mode table d.1-1 eprom programmer socket adaptor package compatible socket adaptor fpt-64p-m03 rom-64sqf-28dp-8l3 fpt-64p-m09 rom-64qf2-28dp-8l4 i/o ram not available not available vacancy program area (prom) program area (prom) 4000 h 7fff h 0000 h 0080 h 0280 h 8000 h ffff h c000 h normal operation epro m mode (corresponding addresses on the eprom programmer)
407 appendix d programming specifications for one-time prom and eprom microcontrollers n recommended screening conditions high-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked otprom microcomputer program. figure d.1-2 "screening procedure" shows the screening procedure. figure d.1-2 screening procedure program, verify aging +150 c, 48 hrs. data verifica tion assembly
408 appendix d programming specifications for one-time prom and eprom microcontrollers d.2 programming yield and erasure this section describes the programming yield and the data erasure on eprom microcomputer. n programming yield all bits cannot be programmed at fujitsu shipping test to a blanked otprom microcomputer, due to its nature. for this reason, a programming yield of 100% cannot be assured at all times. n notes on using and data erasure on eprom microcomputer m erasure in order to clear all locations of their programmed contents, it is necessary to expose the internal eprom to an ultraviolet light source. a dosage of 10 w-seconds/cm2 is required to completely erase an internal eprom. this dosage can be obtained by exposure to an ultraviolet lamp (wavelength of 2537 angstroms ( )) with intensity of 12000 mw/cm2 for 15 to 21 minutes. the internal eprom should be about one inch from the source and all filters should be removed from the uv light source prior to erasure. it is important to note that the internal eprom and similar devices, will erase with light sources having wavelengths shorter than 4000 . although erasure time will be much longer than with uv source at 2537 , nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal eprom, and exposure to them should be prevented to realize maximum system reliability. if used in such an environment, the package windows should be covered by an opaque label or substance.
409 appendix d programming specifications for one-time prom and eprom microcontrollers d.3 programming to the eprom with piggyback/evaluation device this section describes the programming to the eprom with piggyback/evaluation device. n eprom for use mbm27c256a-20tv n programming socket adaptor to program to the prom using an eprom programmer, use the socket adaptor (manufacturer: sun hayato co., ltd.) listed below. inquiry: sun hayato co., ltd.: tel 81-3-5396-9106 n memory space figure d.3-1 memory map of piggyback/evaluation device n programming to eprom 1. set the eprom programmer to the mbm27c256a. 2. load program data into the eprom programmer at 0000 h to 7fff h . 3. program to 0000h to 7fff h with the eprom programmer. table d.3-1 programming socket adaptor package adaptor socket part number lcc-32 (rectangle) rom-32lc-28dp-yg i/o ram not available * program area (prom) program area (prom) 0000 h 0080 h 8000 h ffff h 7fff h 0000 h normal operation (corresponding addresses on the eprom programmer) 0280 h * : in-circuit emulator (ice) tools can be used to access memory range 0280 h ~ 7ffff h
410 appendix e mb89980 series pin states appendix e mb89980 series pin states this section describes the pin states of the mb89980 series in each mode. n pin states in each mode table e-1 pin states in each mode pin name normal operation sleep mode stop mode spl="0" stop mode spl="1" during a reset p00/int20 to p07/int27 port i/o/external interrupt 2 input hold/external interrupt 2 input hold/external interrupt 2 input hi-z/external interrupt 2 input hi-z p10/int10 to p13/int13 port i/o/external interrupt 1 input hold/external interrupt 1 input hold/external interrupt 1 input hi-z/external interrupt 1 input p14 to p17 port i/o hold hold hi-z x0, x0a oscillator input oscillator input hi-z hi-z oscillator input x1, x1a oscillator output oscillator output "h" output "h" output oscillator output mod0 mod1 mode input mode input mode input mode input mode input rst reset input reset input reset input reset input reset input*1 p20/ec port or peripheral i/o hold/peripheral i/o hold hi-z hi-z p21 p22/to p23 p24/rco p25 p26 p27/pwm2 hi-z * 6 p30/pwm1/bz "h" output * 6 p31 input p32
411 appendix e mb89980 series pin states p40 to p47* 2 p60 to p65* 2 p70,p71* 3 port or peripheral i/o hold/peripheral i/o hold hi-z hi-z p50/an0 to p53/an3 com0 to com3* 4 lcd common output lcd common output hold* 5 hold* 5 "l" output seg0 to seg13* 4 lcd segment output lcd segment output table e-1 pin states in each mode pin name normal operation sleep mode stop mode spl="0" stop mode spl="1" during a reset *1: the reset pin can function as an output depending on an option setting. *2: if segment output is selected, the states of these pins are as indicated for pins seg0 to seg13. *3: if common output is selected, the states of these pins are as indicated for com2 and com3. *4: pins com2, com3 and seg0 to seg13 are also used as general-purpose output ports (selected by mask option in mb89983 and by software in mb89p985 and mb89pv980). *5: operate as common/segment output if an lcd controller-driver operating clock is supplied. *6: pin state of p27 and p30 are undetermined until the internal clock starts operation. hi-z: high impedance. pin with a pull-up resistor being selected will go to the pull-up state. spl: pin state specification bit in the standby control register (stbc) spl: the pin set as output holds its state (level) before changing to each mode.
412 appendix e mb89980 series pin states
419 index index the index follows on the next page. this is listed in alphabetic order.
420 index index numerics 16-bit data in ram, storing..................................... 56 16-bit data on stack, storing ................................... 56 16-bit operand, storing ........................................... 56 6-bit ppg function (when 0.5 tinst clock selected for count clock cycle)....................................... 323 6-bit ppg function (when 1/8/32 tinst clock selected for count clock cycle) ................................. 325 8/16-bit timer/counter interrupt ............................. 233 8/16-bit timer/counter interrupt source ................. 223 8/16-bit timer/counter interrupt, register and vector table for ...................................................... 234 8/16-bit timer/counter pin ..................................... 221 8/16-bit timer/counter pin, block diagram of ......... 221 8/16-bit timer/counter register .............................. 223 8/16-bit timer/counter, block diagram ...................219 8/16-bit timer/counter, note on using.................... 244 8-bit pwm timer 1 interrupt source....................... 192 8-bit pwm timer 1 pin........................................... 191 8-bit pwm timer 1 register.................................... 192 8-bit pwm timer 2 interrupt source....................... 198 8-bit pwm timer 2 pin........................................... 197 8-bit pwm timer 2 pin, block diagram of .............. 197 8-bit pwm timer 2 register.................................... 198 8-bit pwm timer interrupt, register and vector table for 203 8-bit pwm timer pin, block diagram of ................. 191 8-bit pwm timer, block diagram of ....................... 189 8-bit pwm timer, note on using ............................ 210 a a/d control register 1 (adc1)............................... 291 a/d control register 2 (adc2)............................... 294 a/d conversion function ....................................... 284 a/d conversion function, activating ...................... 298 a/d conversion function, interrupt for ...................297 a/d conversion function, operation of .................. 299 a/d conversion function, program example for .... 303 a/d converter interrupt source ............................. 290 a/d converter interrupt, register and vector table for . 297 a/d converter pin ................................................. 288 a/d converter pin, block diagram of ..................... 288 a/d converter power supply voltage..................... 287 a/d converter register .......................................... 289 a/d converter, block diagram of........................... 285 a/d converter, note on using ............................... 301 a/d data register (adcd) .................................... 296 accumulator (a)...................................................... 57 activating a/d conversion function....................... 298 activating sense function...................................... 299 adcd register setting for sense function, example of 296 addressing mode ................................................. 388 arithmetic operation instruction ............................ 399 arithmetic operation result bit................................. 59 b branch instruction................................................. 403 buzzer output function.......................................... 374 buzzer output pin ................................................. 377 buzzer output pin, block diagram of ..................... 377 buzzer output register .......................................... 377 buzzer output, block diagram of........................... 376 buzzer output, program example for .................... 380 buzzer register (bzcr) ........................................ 378 c clock controller, block diagram of........................... 87 clock generator ...................................................... 85 clock mode operating state .................................... 93 clock supply function.................................... 162, 308 clock supply function, operation of............... 169, 315 clock supply map ................................................... 83 condition code register, structure of....................... 59 counter function ................................................... 218 counter function, operation of .............................. 237 d dedicated register configuration............................. 57 dedicated register function..................................... 57 display brightness adjustment when internal divider resistor being used .................................... 346 display ram and output pin ................................. 358 e edge detection ..................................................... 252 eprom for use.................................................... 415 eprom microcomputer, note on using and data
421 index erasure on.................................................. 414 eprom mode, memory map in ........................... 412 eprom programmer socket adaptor................... 412 eprom, programming to..................................... 415 external divider resistor ........................................ 348 external divider resistor, using ............................. 348 external interrupt 1 control register (eie1) ........... 258 external interrupt 1 flag register (eif1) ................ 260 external interrupt 2 control register (eie2) ........... 275 external interrupt 2 flag register (eif2) ................ 277 external interrupt circuit 1 function (edge detection) .. 252 external interrupt circuit 1 interrupt source........... 257 external interrupt circuit 1 interrupt, operation of . 264 external interrupt circuit 1 interrupt, register and vector table for ........................................... 263 external interrupt circuit 1 operation, interrupt for 262 external interrupt circuit 1 pin............................... 255 external interrupt circuit 1 pin, block diagram of .. 256 external interrupt circuit 1 register........................ 257 external interrupt circuit 1, block diagram of ........ 253 external interrupt circuit 1, program example for . 266 external interrupt circuit 2 function (level detection)... 270 external interrupt circuit 2 interrupt source........... 274 external interrupt circuit 2 interrupt, register and vector table for ........................................... 278 external interrupt circuit 2 operation, interrupt for 278 external interrupt circuit 2 pin............................... 272 external interrupt circuit 2 pin, block diagram of .. 273 external interrupt circuit 2 register........................ 274 external interrupt circuit 2, operation of................ 279 external interrupt circuit 2, program example for . 281 external reset pin function...................................... 79 external reset pin, block diagram of ....................... 79 extra pointer (ep)................................................... 58 f fpt-64p-m03 and fpt-64p-m09 pin assignment. 32 fpt-64p-m03 package dimension ........................ 34 fpt-64p-m09 package dimension ........................ 36 g general-purpose register area................................ 54 general-purpose register, feature of....................... 65 general-purpose register, structure........................ 63 h handling device, note on ........................................ 48 i i/o area...................................................................52 i/o map.................................................................382 i/o pin and pin function...........................................38 i/o port function ....................................................120 i/o port, program example for ..............................158 index register (ix) ...................................................58 instruction cycle (tinst) ............................................92 instruction list symbol ...........................................386 instruction map .....................................................406 internal divider resistor .........................................345 internal voltage divider resistor, use of .................346 interrupt acceptance control bit ..............................60 interrupt for a/d conversion function ....................297 interrupt for external interrupt circuit 1 operation..262 interrupt for external interrupt circuit 2 operation..278 interrupt for interval timer function ................168, 203 interrupt for interval timer function (watch interrupt) ... 314 interrupt for sense function ...................................297 interrupt level setting registers (ilr1, ilr2, ilr3), structure of ...................................................67 interrupt processing ................................................69 interrupt processing time ........................................73 interrupt processing, stack area for ........................76 interrupt processing, stack operation at start of......75 interrupt request from peripheral function...............66 interrupt request generator ...................................271 interrupt return, stack operation at..........................75 interrupt, wake-up from standby mode by ............115 interval timer function ...........................162, 186, 216 interval timer function (timebase timer), operation of . 169 interval timer function (watch interrupt) ................308 interval timer function (watch prescaler), operation of 315 interval timer function, interrupt for ...............168, 203 interval timer function, operation of ..............204, 235 interval timer function, program example for 211, 246 l lcd control register 2 (lcr2) ..............................356 lcd controller/driver function ...............................342 lcd controller/driver pin.......................................350 lcd controller/driver pin, block diagram of ..........350 lcd controller/driver ram....................................353 lcd controller/driver register................................353 lcd controller/driver, block diagram of ................343 lcd controller/driver, operation of........................360
422 index lcd controller/driver, program example for ......... 371 lcd driving waveform .......................................... 361 lcdc control register 1 (lcr1) ........................... 354 level detection ...................................................... 270 m main clock mode, operation of ............................... 94 main clock oscillation stabilization delay time ........ 96 main clock oscillation stabilization delay time and reset source ................................................. 78 main clock speed-switching function...................... 94 mask option.......................................................... 408 mb89980 series block diagram .............................. 30 mb89980 series features ....................................... 22 mb89980 series product lineup.............................. 24 memory access mode selection operation ........... 118 memory map .......................................................... 53 memory map in eprom mode ............................ 412 memory space...................................................... 415 memory space structure......................................... 52 mode data ............................................................ 117 mode fetch ............................................................. 81 mode pin ................................................................ 81 mode pin (mod1, mod0) .................................... 117 mqp-64c-p01 package dimension........................ 37 mqp-64c-p01 pin assignment............................... 33 multiple interrupts ................................................... 72 o operating state during standby mode ..................... 99 operation during standby mode or operation halt. 208 operation during subclock mode, standby mode, or operation halt ............................................. 242 oscillation stabilization delay reset state ................ 81 oscillation stabilization delay time .................. 96, 116 oscillation stabilization delay time and timebase timer interrupt ...................................................... 168 oscillation stabilization delay time and watch interrupt 314 oscillation stabilization delay time, main clock ....... 96 oscillation stabilization delay time, subclock .......... 97 other instruction.................................................... 405 output waveform during lcd controller/driver operation (1/2 duty ratio) ............................ 362 output waveform during lcd controller/driver operation (1/3 duty ratio) ............................ 365 output waveform during lcd controller/driver operation (1/4 duty ratio) ............................ 368 p package dimension, fpt-64p-m03 ....................... 34 package dimension, fpt-64p-m09 ....................... 36 package dimension, mqp-64c-p01 ...................... 37 peripheral function, interrupt request from ............. 66 pin assignment, fpt-64p-m03 and fpt-64p-m09 32 pin assignment, mqp-64c-p01 ............................. 33 pin function and i/o pin .......................................... 38 pin state after reading mode data .......................... 82 pin state during reset ............................................. 82 pin state in each mode......................................... 416 port 0 and port 1, operation of.............................. 130 port 0 and port 1, structure of............................... 123 port 2, operation of............................................... 138 port 2, structure of................................................ 132 port 3, structure of................................................ 140 port 4, 6 and 7, structure of.................................. 145 port 5, structure of................................................ 152 port-0 and port-1 pin, block diagram of ................ 125 port-0 and port-1 pins........................................... 123 port-0 and port-1 register function........................ 127 port-0 and port-1 registers ................................... 126 port-2 pin.............................................................. 132 port-2 pin, block diagram ..................................... 134 port-2 register....................................................... 135 port-2 register function ......................................... 136 port-3 pin.............................................................. 140 port-3 pin, block diagram of ................................. 141 port-3 register....................................................... 141 port-3 register function ......................................... 142 port-3, operation of............................................... 143 port-4, 6 and 7 pin, block diagram of ................... 146 port-4, 6 and 7 pins .............................................. 145 port-4, 6 and 7 register function ........................... 148 port-4, 6 and 7 registers....................................... 147 port-4, 6 and 7, operation of................................. 150 port-5 pin.............................................................. 152 port-5 pin, block diagram of ................................. 153 port-5 register....................................................... 154 port-5 register function ......................................... 155 port-5, operation of............................................... 157 product lineup, mb89980 series ............................ 24 product selection, point to note for......................... 27 product, different among ........................................ 27 program counter (pc) ............................................ 57 program status (ps)............................................... 58 programming socket adaptor ............................... 415 programming to eprom...................................... 415
423 index programming yield ............................................... 414 pulse counter function, program example for....... 247 pwm 1 compare register (comr1) ..................... 195 pwm 1 control register (cntr1) ......................... 193 pwm 2 compare register (comr2) ..................... 201 pwm 2 control register (cntr2) ......................... 199 pwm timer function.............................................. 187 pwm timer function, operation of......................... 206 pwm timer function, program example for .......... 212 r ram area............................................................... 52 read source when executing bit manipulation instruction .................................................. 407 read-modify-write operation ................................. 407 register and vector table for 8/16-bit timer/counter interrupt...................................................... 234 register and vector table for 8-bit pwm timer interrupt 203 register and vector table for a/d converter interrupt .. 297 register and vector table for external interrupt circuit 1 interrupt...................................................... 263 register and vector table for external interrupt circuit 2 interrupt...................................................... 278 register and vector table for timebase timer interrupt 168 register and vector table for watch prescaler interrupt 314 register bank pointer (rp), structure of.................. 62 register configuration, dedicated............................ 57 register function, dedicated.................................... 57 remote control generation function ...................... 322 remote control generator pin................................ 329 remote control generator pin, block diagram of ... 329 remote control generator register......................... 330 remote control generator, block diagram of ......... 327 remote control generator, note on using .............. 337 remote control generator, operation of................. 335 remote control generator, program example for .. 339 remote control register 1 (rcr1)......................... 331 remote control register 2 (rcr2)......................... 333 reset on ram contents, effect of............................ 81 reset operation, overview of................................... 80 reset source ........................................................... 77 reset source and main clock oscillation stabilization delay time .................................................... 78 rom area .............................................................. 52 s screening condition, recommended......................413 sense function ......................................................284 sense function, activating .....................................299 sense function, interrupt for ..................................297 sense function, operation of .................................300 sense function, program example for ...................304 setting standby mode, note on .............................115 single-chip mode ..................................................117 sleep mode, operation of ......................................101 socket adaptor, programming...............................415 special instruction .................................................392 speed-shift function ................................................94 square wave output function.................................186 square wave output initial setting function, operation of ................................................................239 stack area for interrupt processing .........................76 stack operation at interrupt return...........................75 stack operation at start of interrupt processing.......75 stack pointer (sp) ...................................................58 standby control register (stbc) ...........................105 standby mode .........................................................98 standby mode and interrupt, changing to .............115 standby mode or operation halt. operation during 208 state transition diagram 1 (option power-on reset, two clocks) 107 state transition diagram 2 (option without power-on reset, two clocks) 110 state transition diagram 3 (on clock option)..........113 stop mode, operation of........................................102 storing 16-bit data in ram ......................................56 storing 16-bit data on stack ....................................56 storing 16-bit operand.............................................56 subclock mode, operation of...................................94 subclock mode, stanby mode, or operation halt, operation during .........................................242 subclock oscillation stabilization delay time............97 system clock control register (sycc), structure of.90 t temporary accumulator (t) .....................................58 timebase timer control register (tbtc) ................166 timebase timer function ........................................169 timebase timer interrupt and oscillation stabilization delay time ...................................................168 timebase timer interrupt, register and vector table for 168 timebase timer, block diagram of..........................164 timebase timer, note on using ..............................171
424 index timebase timer, operation of................................. 169 timebase timer, program example for...................173 timer 1 control register (t1cr)............................. 224 timer 1 data register (t1dr)................................. 229 timer 2 control register (t2cr)............................. 227 timer 2 data register (t2dr)................................. 231 timer stop and restart ........................................... 241 transfer instruction................................................ 395 v vector table area .................................................... 54 w wake-up from standby mode by interrupt............. 115 watch interrupt.............................................. 308, 314 watch interrupt and oscillation stabilization delay time 314 watch mode, operation of..................................... 104 watch prescaler control register (wpcr)............. 312 watch prescaler interrupt, register and vector table for 314 watch prescaler, block diagram of ....................... 310 watch prescaler, note on using ............................ 317 watch prescaler, operation of............................... 315 watch prescaler, program example for................. 318 watchdog timer control register (wdtc).............. 179 watchdog timer function ....................................... 176 watchdog timer, block diagram of ........................ 177 watchdog timer, note of using .............................. 183 watchdog timer, operation of................................ 181 watchdog timer, program example for ................. 184
cm2 5 - 1 01 4 1-1e fujitsu semiconductor ? controller manual f 2 mc-8l 8-bit microcontroller mb89980 s e ries hardware manual m a rc h 2 0 0 0 th e fir s t e d it i on p u b l i s h e d fujitsu limite d electronic devices edited tech n ica l com m unication d e pt.

fujitsu semi c onductor f2mc-8l 8-bit microcontroller mb89980 series h ardware manual

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